Vertical system integration

ABSTRACT

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

The diversity of circuit function and operational requirements thatunderlay the implementation of a broad range of integrated circuitapplications including what is commonly referred to as a SoC [System ona Chip] demand widely varying semiconductor fabrication processes and/ortechnologies without further consideration being given to theintegration of optical and MEMS technologies with those semiconductortechnologies. Limitations on the electronic industry's capability tomeet these ever greater demands has made the implementation of numerousintegrated circuit and SoC products impossible or beyond acceptablemanufacturing costs.

The Vertical System Integration (VSI) invention herein is a method forintegration of disparate electronic, optical and MEMS technologies intoa single integrated circuit die or component and wherein the individualdevice layers used in the VSI fabrication processes are preferablypreviously fabricated components intended for generic multipleapplication use and not necessarily limited in its use to a specificapplication. The VSI method of integration lowers the cost differencebetween lower volume custom electronic products and high volume genericuse electronic products by eliminating or reducing circuit design,layout, tooling and fabrication costs.

The VSI invention achieves its novel methods of integration through highprecision alignment and stacking of component layers, fine grainvertical interconnections, thin flexible circuit substrates fabricatedusing stress-controlled dielectrics and low temperature component layerbonding. The VSI integration methods are fabrication methods that areindependent of the fabrication process methods used in electronic oroptical circuit fabrication or MEMS fabrication.

The VSI invention enables the integration of systems or subsystems as asingle die or VSI IC which would otherwise be collections of multipleplanar ICs, optical ICs, passive circuit devices and or MEMS. A VSI ICis a stack of closely coupled device or component layers the majority ofwhich are less than 50 μm thick and typically less than 25 μm thick. TheVSI invention for vertical integration fabrication of planar electronic[passive and active], optical or MEMS device layers enables on demandfast turn circuit fabrication through the use of an inventory ofpreviously fabricated generic VSI IC or device layers in combination ofvarious proprietary IP generic device layers to achieve custom circuitrywhich, heretofore, would require at a minimum a new circuit design,layout and masking before consideration of the planar circuit processintegration incompatibility of various device elements.

The VSI fabrication methods enable significant cost and power reductionand performance enhancement through higher levels of integration withhigher circuit yields than are presently possible with planar circuitfabrication processes. VSI IC device layers are interconnected by highdensity vertical interconnections which are scalable so that they can becompatible with the on going decreases of circuit fabrication geometriesused in horizontal interconnections of the planar device layers. The VSImethod for high density vertical interconnection is enabled throughwafer to wafer bonding alignment methods capable of precisions of lessthan 25 nm.

The VSI fabrication methods enable the integration as one IC or die thatare currently system assemblies of discreet circuits with the benefitthat performance limiting circuit interconnect structures such as longon-IC interconnections, IC carriers and sockets, PCBs and PCB edgeconnectors are eliminated. The VSI invention enables the reuse of postfabrication or inventory circuit device layers for multiple ICapplications. The primary benefits of the VSI technology is a reductionin complexity of IC manufacturing, testing, packaging and an increasedin circuit yield resulting in a nominal reduction in manufacturing costsof approximately 10× and commensurate with an approximate nominal 5×increase in net circuit operating performance.

The VSI invention enables the implementation of SoC circuits whichpresently cannot be manufactured for the commercial or consumer marketsdue to technological or manufacturing costs limitations. This is beforeconsideration of the present high costs associated with custom circuittooling, large die size or the low production quantities.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to methods for making closely coupledclosely aligned stacked integrated electronic circuits, optical circuitsand MEMS. In particular, the present invention relates to methodsspecific to fabrication integration, yield enhancement, performanceenhancement, power dissipation reduction and cost reduction.

2. State of the Art

Manufacturing Integrated Circuit [IC] methods are most notable for anexponential rate in the integration progression of electronic devicesper unit area, consistently doubling approximately every 18 months overa short forty year history. These manufacturing methods are remarkablefor their abilities of increasing circuit performance whilesimultaneously reducing circuit cost, power and size, and as a resultICs have contributed in no small measure to today's modern way of life.

The integration progression has repeatedly enabled the making of ICsthat were not possible or practical only a few years earlier. Whatbefore prevented the practical implementation of circuits with 100,000transistors due to excessive power dissipation or low fabricationyields, the integration progression has now enabled practical yields ofcircuits with 100,000,000 transistors and at much lower powerdissipations despite the dramatic increase in transistor count. Theintegration progression has made possible the expectation that ICs withmore than 1 billion transistors will be in wide spread common use withinthe next three to four years.

The ultimate and widely understood objective of the IC integrationprogression is to reduce all electronic systems or subsystems composedof multiple ICs to one IC. This ultimate IC is often commonly referredto as a SoC [System on Chip]. The result of this objective is ever lowercost of manufacturing, higher performance, and hopefully therefore, agreater end user utility and social benefit. FIG. 1 shows in crosssection a conventional planar IC composed of number of IP [IntellectualProperty] circuit blocks 1 a which are interconnected by numerous layersof horizontal metal interconnect or wiring 1 b.

Electronic systems and subsystems made from assemblies of separateplanar ICs are performance or cost reduction limited foremost by theimplementation means for off-circuit or off-chip interconnections orI/Os. The performance and cost reduction limitations due to IC I/Oresult from manufacturing restrictions in the number of I/Os an IC mayhave, the cost of packaging, the significantly lower transmissionperformance of off-circuit connections versus on-circuit connections andthe higher power dissipation required for off-chip signal transmission.Further, there is not presently planar IC fabrication technology thatwill allow the integration onto one planar IC for all of thesignificantly different IC fabrication processes used to make theelectronic components of widely used products such as PCs, PDAs or cellphones. This is likely to remain so for the foreseeable future, becausepast demand for greater capabilities from such electronic products hasresulted in greater divergence of the IC fabrication processes used toimplement the various types of ICs from which they are made.

The usefulness of the integration progression is now strongly challengedby the growing complexity in the design, and logical and physicalverification development and test efforts required to bring ICs tomarket. The wide spread incorporation of previously designed or off theshelf logic functions referred to as IP [Intellectual Property] is anexample of efforts being taken to address IC design and developmentcomplexity. However, the usage of ever greater numbers of IP placementsacross an IC has resulted in greater logical, physical and manufacturinginterconnection complexity.

The integration progression rate has changed the relationship of theprimary cost structure components for making ICs. The cost of testingICs is now approaching and in a number of cases exceeding IC fabricationcost and the cost of IC packaging ranging from 25% to several times ICfabrication cost. The cost dominance of test and packaging over ICfabrication increases with each generation of IC fabrication technology.It is becoming clear that IC manufacturing methods that reduce throughIC integration techniques the cost of test and packaging are of mostimportance.

The integration progression is presently challenged by the need formethods to integrate as a single die not only active electronics, butalso passive electronic devices, optical devices and MEMS[Micro-Electro-Mechanical Systems]. This need is particularly evident innetworking and telecommunication equipment where the switching ofoptical signals through the conversion of optical signals to electronicand back, to optical or electronically controlled MEMS of opticalmirrors are used. But also in consumer products such as video devicesthat use imaging arrays which need higher integration of processingelectronics and memory or wireless communication devices which needgreater integration of analog and passive circuitry.

The primary drivers of the integration progression of planar ICmanufacturing have been circuit feature size reduction throughfabrication process methods and increased wafer or substrate diameter.Volume production process fabrication methods for the dominate CMOSsemiconductor technology has presently reached feature sizes of 0.12 μm[120 nm], and wafer sizes of 300 mm [12 inches]. Methods for formingstacked ICs or stacked IC structures have been demonstrated and areexpected to become one more of the primary drivers of the IC integrationprogression.

IC stacking methods can be broadly classified as:

-   -   1. Package driven stacked ICs.    -   2. Process driven [design and fabrication] stacked closely        coupled ICs.

The stacking of ICs through various packaging methods or package drivenstacking has a long and varied application history that goes back atleast twenty years. A recent article published in the IEEE Spectrumentitled “Packages Go Vertical” by Harry Goldstein, August 2001, pages46-51, is one representative summary of the more recent methods of 3Dpackaging of Integrated Circuits. The primary benefit of package drivenstacking of ICs is reduced physical volume, implemented through the useof conventional ICs with various methods of forming peripheralconnections from the I/O contacts of each IC to a common set oftermination contacts of the package envelop enclosing the ICs.

The stacking of ICs through process drive methods, typically requirescustom designed ICs and wafer level processing steps. The primarybenefits of process driven IC stacking are increased performance withsimultaneous reductions of cost, size and power. Process driven stackedICs can be generally characterized by the following process steps:

-   -   1. Wafer level bonding with a bonding material thickness of a        few microns or less.    -   2. Thinning of wafer circuit layers to less than 50 μm and        typically less than 25 μm and less than 15 μm.    -   3. Vertical through the circuit layer substrate interconnections        or interconnections that are internal to the IC stack.

Process driven wafer stacking fabrication in the above manner willherein also be referred to as Closely Coupled stacked integratedcircuits. The Closely Coupled stacked integrated circuit layers of theinvention herein are thinned to facilitate the fabrication of fine grainvertical interconnections passing through the circuit layers andsubstantially flexible, and wherein these layers are preferablyfabricated using low stress or stress controlled dielectric materials.The primary objective of closely coupled wafer stacking is to enhancethe integration progression of IC fabrication beyond that possible withexisting planar wafer process fabrication methods and wafer diameter.Closely coupled stacked IC prior art by the inventor and referred to as3DS [Three Dimensional Structures] are U.S. Pat. Nos. 5,915,167,6,208,545, 6,133,640, 6,551,857, 6,563,224, 5,985,693 and 5,654,220.

Closely coupled wafer bonding requires wafer to wafer alignment prior tobonding. Equipment presently available has the capability for ±1 μmwafer to wafer alignment. By comparison horizontal interconnectionminimum pitch is 0.15 μm [150 nm] with current state of the artsemiconductor processes. The horizontal routing efficiency throughvertical interconnections is determined by wafer to wafer alignment, andis fundamentally important to the scaling of fine grain verticalinterconnections to maintain compatibly with reducing horizontalinterconnection geometries.

The state of the art for completed or fabricated planar ICs has andpresently results in the expectation that the utility of a fabricated ICdoes not allow its reuse for subsequent IC integration in a single dieor single IC. This is to say that subsequent integration ofpost-fabricated planar semiconductor circuitry with other fabricated ICsthat would result in device and interconnection integration densitiesthat are the same or similar to any of the planar ICs being integrated,and therefore, providing the well known attendant benefits of single ICintegration, is no longer possible. Therefore, any and all subsequentcircuit design changes or additions [placement of circuitry orhorizontal interconnect routing layers] to a completed planar ICrequires the IC be remade, requiring at a minimum revalidation ofelectrical and functional operation of the circuit, the remaking of masktooling, circuit fabrication and in most cases the obsolescence ofprevious circuit inventory. This is a clear and significant restrictionon the control of cost in the development, manufacturing and inventorymanagement of planar ICs. Conversely, having the ability to inventoryfabricated or complete circuitry which can subsequently be integrated atthe IC or die level presents a opportunity for cost savings that affectsall aspects of IC development and manufacturing, and extends the rangeof intended end use applications beyond that presently possible.

Planar Circuit Integration Progression Limitations

There presently exists numerous limitations to the integrationprogression of planar ICs, some of these limitations which are:

[1] Die Size in Fabrication, Complexity and Performance

The IC Integration Progression is limited by die size. The die size ofplanar circuits is limited by current semiconductor fabricationlithographic technology. Die size fabrication lithographic limitationsstem from the maximum imaging field size of present semiconductorlithographic processing equipment. The often sought end objective formost electronic products or applications composed of multiple ICs is tointegrate the ICs into a single chip solution referred to generically asa SoC [System on Chip]. The limits of circuit integration manufacturingare feature size and lithographic stepper reticle size [maximumlithographic image size] and yield. At this point in time production ICfeature size is approaching 0.12 μm and stepper reticle demagnificationsize is approximately 25 mm by 30 mm which enables presently a die sizelimit of approximately one square inch.

Larger planar ICs, those greater than 100 mm², that are fabricated withlithographic processes less than 0.15 μm are limited in performance bythe distances across the surface of a die or chip of such size resultingin the use of additional circuitry to amplify signals that must travelthese greater distances. Adding further to the complexity of long signalline propagation is the use of lower voltage levels [such as 1.5v whenusing 0.15 μm fabrication technology] which result in lower signalstrength, and stronger parasitic electronic effects due to the use ofsmaller lithographic geometries. And further as a result of large ICsand smaller lithographic geometries, skewed timing of signals whichresults from the varying distances of circuit sources makes an everpresent demand for more precise circuit timing analysis and attendantcircuit design compensations necessary to reduce planar circuit signalskew sufficiently to bring the circuit into acceptable operating rangeswithout too great a reduction in net circuit performance.

[2] Levels of Interconnections and Substrate Leakage Limit DeviceFabrication Density and the Use of Complex IP Blocks

The IC Integration Progression has now reached a minimum circuit devicefeature size of 0.15 μm [150 nm] in volume production. The end of the ICintegration progression is now anticipated to be something approaching afeature size of approximately 20 nm. An increase in circuit density ofapproximately 36 times. However, such circuit density gains will bedifficult to achieve or to implement their effective use withoutadditional horizontal interconnect layers and new methods of powerreduction or utilization necessary to drive a greater number of lowvoltage signals long distances over the surface of planar circuits. Inorder to implement greater circuit densities resulting from smallercircuit devices, a comparable reduction in the geometries ofinterconnections and an increase in the number of interconnection levelsmust be achieved. Reduction in power dissipation is necessary to preventpower dissipation from becoming a limitation on IC IntegrationProgression. Reduction in transistor substrate leakage could reducecurrent power dissipation by approximately 50%.

The IC Integration Progression is limited by the number ofinterconnection levels that can be used in a circuit design. The numberof horizontal wiring levels of a planar IC is limited by manufacturingprocesses, presently nine [9] layers, which in turn limit theintegration density of an IC design. Smaller active device circuitgeometries and the frequent incorporation of hardwired IntellectualProperty [IP] in the design of a circuit increases the wiring orinterconnection complexity between those IP circuit elements to eachother and the rest of the circuitry of an IC. The design of most ICs andcertainly most large complex ICs incorporate IP circuitry into theircircuit designs in order to save the time and human resources that wouldotherwise be required in duplicative development of such circuit IPs.Increased die size and greater use of IPs results most often in anincrease in the planar [horizontal] routing interconnection complexity.This interconnect complexity results in more layers of interconnectionsnecessary to complete a circuit's local and global wiring networks. Thisinterconnect complexity is proportional circuit size, resulting inhigher manufacturing costs.

[3] Interconnection Design Complexity

The integration progression is physically accomplished by the making ofever smaller circuit devices and through the fabrication of denser anddenser interconnections or wiring. Design of most planar circuits possesthe challenge of routing interconnections from one circuit block orfunctional group of transistors to another circuit block and thentypically to the portion of the die of the circuit where I/O pads orcontacts are formed for off circuit or external connections. Thesehorizontal interconnections take the form of successive layers firstinterconnecting adjacent circuit devices, then progressing to theinterconnection of ever more distant circuit blocks of the circuit.These interconnection layers are themselves connected by structurescalled vias, or wiring connections typically of less than 1 μm inlength. These horizontal circuit interconnections have proved to be thegreatest challenge in the design of large circuits resulting in anon-stop evolution of more sophisticated automatic interconnect routingsoftware tools for completing what is called the physical IC design, andthe addition of more and more interconnect layers presently at nine [9]and anticipated to exceed twelve [12] by 2005.

[4] Limits of SoCs, ASICs and FPGAs

The IC Integration Progression has lead to efforts to incorporate allthe ICs of a system onto one chip, resulting in the reference to suchICs as SoCs [System on Chip]. However, achieving the SoC goal is greatlyrestricted by the limited ability of the semiconductor industry tofabricate single ICs consisting of multiple semiconductor processes[such as 0.5 μm analog and 0.18 μm logic or DRAM processes] or multiplesemiconductor technologies [such as SiGe and GaAs, InP, GaN, etc.].

Similar problems face the more traditional and familiar ASIC and FPGA[Field Programmable Gate Arrays] or CPLD [Complex Programmable LogicDevices] products. The limitations of ASICs are design complexity due totheir relentless growth in size, and a long and costly of productdevelopment process. The well established benefit of ASIC integrationhas now also become a limitation that requires re-verification andretooling of the entire circuit irregardless of the size of a designchange and followed by prototype fabrication delays measured in months.

The alternative to ASICs are FPGAs or CPLDs with the advantage of a veryshort product development process, but with the distinct disadvantagesversus ASICs of higher unit circuit cost, lower performance and lowergate density. The lower performance and lower gate density of FPGAsfollows from the interconnect complexity required to supportprogrammable function blocks and the on chip programmable routinginterconnections for programming of the function blocks.

The development of SoCs, ASICs and FPGAs circuits has become increasingcapital intensive in terms of facility support and large numbers ofhighly trained personnel. The IC integration progression can onlyguarantee that this trend will continue, making the development of thesecircuits the exclusive domain of a few large established companies withthe result of lessening product diversity, competition and the wellestablished economic vitality that flows from the innovation of smallenterprise. The result of the current trends of the IC integrationprocess is the loss of greater diversity due to the growing capitalbarrier to market entry, this cannot be in the long term public bestinterest.

All planar circuits are made from a custom mask set, where a mask setconsists of typically 16 to 32 lithography masks. A single change to onecircuit device or the its wiring connections in a circuit design of 10sof millions of circuit devices will result in the remaking of several orall masks for a planar IC. This in turn results in a requirement fortiming simulation analysis of the circuit to determine anew it operatingcharacteristics and if a failure condition has been created by thechange. The operational simulation process or IC physical validationprocess presently requires the majority of development effort in thedesign of most ICs. This effort is growing with the rate of integrationprogression.

[5] Intellectual Property

IP [Intellectual Property] in the semiconductor circuit design industrytypically refers to previously designed integrated circuit blocks thatcan be incorporated into a circuit design with only modest levels ofadditional engineering design effort. IPs are often an item of trade andare leased for incorporation into a circuit design. Some examples of IPsare microprocessors, DSPs, PCI bus interfaces and arithmetic functions.The value of IP is its ability to reduce IC development costs by itsuse, however, the reuse of IP only offers circuit design cost savingsand does not extend savings to IC fabrication.

[6] IC Inventory Management and Reuse

Circuit design changes to an ASIC or any IC results in the need to makenew masks and potentially the creation of devalued or obsolete[valueless] inventory of those circuits made from the current and nowoutdated mask set. A design change requires the remaking of one or moremasks. New masks are expensive, and in large planar circuit designs madewith complex processes they also can result in the introduction of newcircuit defects, or due to large mask size reduced IC yield. ASICinventory is a serious problem which comes in three forms: wafers, baredie and packaged circuits. Circuit inventory is most often held in waferform for cost reasons, it represents unfinished goods at a lower valuebut can be quickly turned into the finished goods of bare die orpackaged die, however, circuit wafer inventories often take severalmonths to replenish. This is a difficult unfinished goods managementchallenge. Once circuit wafers are fabricated, a change in IC demand ora circuit design change can render these circuit wafers of little or novalue. The ability to reuse such obsolete circuit wafers is often not anoption even though the majority of the area of each die on the wafer isoften unaffected by a circuit design change; this being even more thecase the larger the planar circuit design. The challenge for ICintegration is to reduce mask complexity for large circuit designs andto find methods for reuse of unaffected circuit area due to designchanges.

[7] Power Limitations Due to Substrate Leakage and I/Os

Power dissipation of large ICs have increased significantly with theIntegration Progression such that high performance circuits exceed 100watts of power. Such high thermal heating of ICs limits the performanceand useful life of the IC. The primary sources of IC power dissipationfor most high performance ICs is from substrate leakage and high I/Ocounts. Substrate leakage is the passage of current between source anddrain while the transistor is in the off state. Substrate leakage isincreasing with decreasing circuit feature size and is expected to bemore than 30% of IC power dissipation for fabrication processes below130 nm. The power dissipation from I/O drivers are well known, but theincrease in the number of I/Os for advanced ICs is expected to exceed1,000 by 2004 and is a limit on the use of the IC technology.

[8] Circuit Yield Enhancement

ICs of greater than 100 mm² often resort to redundant or spare circuityield enhancement methods. Such methods have proven successful in only afew higher volume production circuit types such as DRAMs and PLDs. Thesemethods have been tried with little success in planar custom logiccircuits by such companies as TRW in the 1980s and Trilogy Corporationfounded by Dr. Gene Amdahl in the 1970s. These attempts failed dueprimarily to the limitation of circuit design automation software toolsand available capacity of horizontal interconnections. The integrationprogression beyond 0.15 μm [150 nm] circuit device feature size willreduce the size or foot print of large and complex IP circuit functionssuch as microprocessors, DSPs or graphics processors to enable sparingas the simple solution to planar circuit defect resolution, however, thedesign complexity of interconnection layout and the capacity ofhorizontal interconnection is still a challenge for generalizedimplementation methods for these types of circuits.

The testing of ICs under normal and stressed conditions is challengingproblem. External testing of ICs by ATE [Automatic Test Equipment] ispresently the primary means of determining if a circuit is defective.This testing procedure is complex and lengthy and can result in failureto detect a defective operating condition.

Further, most circuits under go a procedure called burn-in. Variousfailure conditions of an IC only occur under temperature or voltagestressing, or after some lengthy period of operation. The burn-inprocedure is the means used to provide this type of testing, however,the burn-in procedure lacks the full speed functional testing proceduresof ATE testing, and therefore, can result in failure to detect adefective operating condition.

[9] Lithographic Limitations

Production semiconductor lithographic tools use masks in the form ofimaging reticles which image or print one or more die onto a wafer perlithographic exposure. Lithographic exposures are repeated until thewafer or substrate is completed. The reticle is limited in its abilityto image circuitry on a wafer in one exposure to an approximate area of25×30 mm, and therefore, the largest planar IC that can be made islimited to the maximum imaging area of the reticle of the lithographicsystem. The production tooling for making an IC consists of a set ofmasks. The number of masks per mask set is dependent on the complexityof the process being used and nominally vary from 16 to 32 masks. Anydesign change to a circuit results in the remaking of one or masks ofthe ICs mask set. Changing the placement of an IP circuit block orinterconnection busing structure will result in the remaking of all ofthe masks of the ICs mask set. The cost of making an IC mask set hasincreased sharply with mask geometries below 150 nm, and is limiting thedevelopment of ICs with smaller market volumes.

[10] MEMS [Micro-Electro Mechanical Systems]

MEMS devices are a rapidly developing manufacturing technology which usesemiconductor fabrication processes but has only limited compatibilityfor integration with IC fabrication processes and technologies. MEMStake the form of such devices as accelerometers, DMD [Digital MirrorDevices], video imaging sensors, micro-switches and micro-gyros. Thecapability to integrate microprocessors, memories and wireless circuitryto name a limited few IC types would greatly expand the application,performance and capability of MEMS devices.

[11] IC Test Complexity and Cost

The complexity of circuit test has risen steadily with the increase ofcircuit integration and higher circuit performance. The common use ofgeneric programmable external test ATE systems has proven to be limitedin their ability to do exhaustive IC testing due to access to internalcircuitry blocks and the economic constraints of their use due to theirhigh cost. It is presently the case that for many complex circuits, ATEsystem testing is the largest cost component in the manufacture of suchcircuits. The methods that incorporate self test circuitry have met withlimited success because these methods add to the already complex effortof planar circuit design and layout. Additionally, neither of these twotest method approaches provides the ability to validate the fulloperational integrity of a circuit during its useful life in either astand-by means or a dynamic means.

[12] Information Transmission

The transmission of information between ICs is restricted by thefrequency of transmission between ICs and the data path width betweenICs. The use of ever higher internal IC clock rates now exceeding 1 GHzmakes this problem more pronounced. A single IC to IC connection [wire]using a transmission frequency of 500 MHz requires complex andcustomized transceiver logic with disadvantages in power and space.Secondly, these disadvantages coupled with packaging I/O restrictionsimpose a practical limitation on data path widths of 256 connections andon the length of the data path.

[13] Custom ICs Versus Generic Application ICs

The IC integration progression has resulted in reducing the pertransistor cost of manufacturing to near zero cost, however, the cost ofdesign and fabrication tooling have risen to unanticipated high levelsand are expected to continue to do so. Low volume custom circuit demandis being strongly challenged by higher volume generic applicationcircuits. There is still demand or a need for custom designed circuitsmade with state of the art IC fabrication process, but their lowproduction volumes are making them prohibitively expensive. This is aproblem for the semiconductor industry as a whole, because innovationalmost always comes from small or startup businesses with new ways ofusing established technologies, such increasing demonstration costs fornew higher risk IC designs will certainly have a negative effect oninnovation.

Summary of Primary Improvement Objectives of the VSI IC Invention VersusPlanar ICs

The primary improvement objectives of the VSI invention disclosed hereinover current planar IC design and manufacturing processes are higherperformance and lower cost.

Higher performance:

-   -   1. Smaller die size that is independent of circuit size.    -   2. Integration of disparate fabrication technologies by circuit        layer.    -   3. Single die level integration that is independent of circuit        size and process technologies used.    -   4. Shorter horizontal interconnection lengths through the use of        vertical interconnections.    -   5. Shorter horizontal lengths through the use of smaller die        size.    -   6. Greater of planar circuit layer to circuit layer        interconnection density through fine grain vertical        interconnection.

Lower cost:

-   -   1. Smaller die size.    -   2. Fewer IC packages.    -   3. Fabrication process of self packaging.    -   4. Lower I/O pin count per package.    -   5. Internal self test logic.    -   6. Enhanced Yield.    -   7. Lower design complexity through smaller die size.    -   8. Design and fabricated circuit reuse through standardized fine        grain vertical interconnection physical foot print sizes and        placement.    -   9. Automated design of large scale and fine grain circuit        reconfiguration and failure replacement by circuit redundancy.

SUMMARY OF THE INVENTION

The invention is a general method for custom integration fabrication ofa broad range of electronic, optical and MEMS fabrication processes andtechnologies including the sensing and processing of information. Thisinvention is a general method for vertical integration into a single dieor component of incompatible and disparate electronic, optical and MEMSmanufacturing processes. This invention is herein referred to asVertical System Integration [VSI] or the VSI invention. Variousadditional inventions are also disclosed that are enabled through use ofthe VSI invention, provide novel means for enabling the VSI invention orare in novel combination with the VSI invention as a preferredembodiment.

The VSI invention provides novel means for achieving through verticalintegration the multiple primary objectives of lower manufacturing cost,higher performance and smaller size for electronic, optical and MEMSdevices. The VSI invention enables the integration into a single IC orcomponent electronic circuit, optical circuits and MEMS devices ascircuit or device layers, which are presently individually packaged andassembled onto a supporting interconnection structure such a PCB[Printed Circuit Board]. The circuit or device layers of the VSIinvention are preferably thin and flexible wherein these layers arefabricated using low stress or stress controlled dielectric materials.The VSI method of device integration is markedly different from planarIC methods which have demonstrated success only where deviceimplementation does not require multiple dissimilar circuit fabricationprocesses, more than one semiconductor technology or a circuit devicedie size that is beyond available IC fabrication manufacturingcapabilities. Since the circuit layers of the VSI invention not onlyconsist of electronic active device circuitry, but also electronicpassive device circuitry [such as inductors, resistors, capacitors,associated interconnections or wireless transmission antennas], activeand passive optical circuitry with associated wave guideinterconnections and mechanical devices generically referred to as MEMS[Micro Electro-Mechanical Systems], the broader terms VSI Layer orDevice Layer will be used to inclusively refer to layers of the VSIinvention as being anyone of an electronic, optical or mechanical layer.A completed stack of VSI layers will be referred to as a VSI componentor a VSI circuit or a VSI IC. Other terminology used to refer to a VSIlayer are circuit layer, EO [Electro-Optical] layer, MEMS device layer,IC layer or VSI component layer, wherein the term circuit layer will beused to reference both electronic or optical VSI layers, and VSIcomponent layer will be used to reference all VSI layer types. Theindividual active or passive circuitry used in a die or circuit layerare referred to as circuit devices or circuit elements, examples ofwhich are electronic transistors, magnetic memory cells, opticalamplifiers, resistors or inductors. The unit of VSI fabrication ingeneral is a substrate consisting of an array of ICs, passive circuitinterconnection patterns or MEMS devices fabricated on it, it is thesewafers or substrates that become the circuit layers of a VSI wafer orsubstrate stack, and from which after a dicing process step, individualVSI components or ICs are realized.

The VSI invention integrates electronic circuits, optical circuits andor MEMS devices through a stacking fabrication process where circuit ordevice layer wafers or substrates, made with similarly dimensionedarrays of electronic, optical or MEMS components, are precisely alignedand bonded together, the substrate is thinned as needed to enablevertical access to circuit layer elements, electronic conductors oroptical wave guides for subsequent circuit element or interconnectstructure fabrication where upon the subsequent device layers are addeduntil the substrate stacking is completed. The individual VSI componentsare then cut or sawed from their wafer or substrate stack in a mannersimilar to the way today's conventional planar ICs are cut from wafersubstrates on which they are fabricated.

The VSI invention is a means for fabrication of customized orapplication specific single die IC components with the requirement forlittle or no custom circuit design and fabrication tooling. Today, allplanar ICs require circuit design, layout and mask tooling before theycan be fabricated. The VSI invention achieves this novel result in itspreferred embodiment by making integrated VSI components of electronic,optical circuit layers and or MEMS device layers from generic librariesof VSI inventory circuit and or MEMS substrates with completed physicaldesigns, wherein an application specific IC results from the selectionand or order or number of the VSI library layers, or in combination withthe specific use of one or more types of programmable VSI circuitlayers. This aspect or embodiment of the VSI invention enablesapplication specific customization to be the result of only the VSIfabrication process and absent the specific custom design of a circuitlayer. Another embodiment the VSI invention is the fabrication of a VSIcomponent or IC from a inventory circuit substrates and circuitsubstrates of completed physical application specific design intendedonly for use in one or limited number of VSI component part types. Thisis in clear difference to present ASIC or custom circuit integrationmethods wherein all device components from an IC library requireindividual placement and layout to be performed to complete theintegration of the planar IC, and therefore, any change or addition to aplanar IC requires design changes and fabrication of mask tooling forthe whole or all of the planar IC.

Although such terms as ASIC and ASSP [Application Specific StandardProduct] are used to refer to planar ICs of application specific designsand such terms as DSP, μP and DRAM are not used to refer to customcircuits, this distinction relates to the production volumes of suchcircuits where volumes for ASICs are low and volumes for DRAMs are high;however, there is no distinction between these various circuit typeswith respect to circuit layout and fabrication tooling, these items arecustomized to the circuit no matter its volume, whereas VSI componentsor ICs with customized or application specific capabilities can befabricated without requiring circuit layout and fabrication toolingspecific to the capacities or capabilities of a VSI component. It isalso a distinction of VSI components or ICs versus conventional planarICs that a portion of a VSI circuit can be customized and withoutrequiring the custom layout and tooling for the whole or all of the VSIcomponent; this is the case wherein certain VSI circuit layers, but notall circuit layers, with application specific functions are fabricatedas custom design layouts and requiring fabrication tooling of the layersof the VSI IC; such VSI circuit layers could be referred to as VSI ASICcircuit layers. It is a distinct advantage of the VSI invention that theincorporation of hardwired customized or application specificcapabilities or functions or design changes of a VSI circuit layer orlayers affect only a portion of the VSI circuit and do not result incircuit layout related design considerations and fabrication tooling ofthe whole circuit as is the case with all planar circuit fabricationtechnologies.

Further, as a result of the aspect of the VSI invention enablingfabrication of circuitry with a minimum of or no design layout andfabrication tooling efforts, the well known cost distinction that existspresently to the advantage of ICs of high volume production versus ICsof low volume is significantly reduced due to the VSI inventioncapability to fabricate many low volume VSI ICs in an additive orcommingled manner with high volume VSI ICs achieving similar costsavings, which is now only a benefit of the high volume fabrication ofsingle planar circuit. This distinction of the VSI invention enables thedesign and fabrication of electronic and optical integrated circuitsfrom a library of previously completed physical IC designs andfabricated circuit substrates without placing a predetermined constrainton the size, circuit functions, capacities and technologies of theintegrated circuit; this is a benefit that reduces the fabricationcomplexity and cost of an integrated circuit in an inverse relationshipto circuit capacity and capability.

The VSI IC fabrication process of the VSI invention produces CloselyCoupled circuit layers. The term Closely Coupled means that the circuitlayers are sufficiently thin to enable fine grain verticalinterconnections between each circuit layer and that the interconnectionlengths of electronic or optical interconnections connecting thecircuitry on the various VSI circuit layers of a VSI component are lessthan or equal to the total thickness of the VSI layers making up thestack of the VSI circuit layers of a VSI component. Theseinterconnections are routed vertically between VSI layers and interiorto each VSI circuit layer passing through any number of circuit layerswith or without making a signal contact to circuitry on them. Further,Closely Coupled means that the interconnection density between VSIlayers is fine grain and significantly greater than what is possiblewith present off circuit interconnection densities between coplanarcircuits, wherein the vertical interconnection pitch of Closely CoupledVSI layers is preferably less than 4 μm and preferably less than 2 μmand less than 1 μm. Interconnect lengths between two physicallyadjoining VSI circuit layers can be less than the combined thickness ofthese adjoining VSI circuit layers, since the typical thickness of a VSIlayer is less than 50 μm and often less than 15 μm, VSI layer to layerinterconnection lengths can be less than 30 μm and less than 15 μm. Thethickness of a VSI component is typically less than 4,000 μm and in mostembodiments is less than 200 μm and can be thinner than 100 μm. The twoprimary characteristics of Closely Coupled VSI circuit layers areelectronic or optical vertical interconnections which are [1] of similarpitch density to that of the horizontal interconnections of a circuitlayer, and [2] provide the shortest interconnection length between anytwo active or passive circuit device elements that are not both locatedon the same VSI circuit layer.

Closely Coupled VSI circuit layers enable improved IC performance due tothe shorter circuit layer to circuit layer vertical connection lengthsand also due to the VSI enabled capability to hold constant or reduceVSI layer die size [circuit layer area] while increasing the totalcircuitry surface area by increasing the number of VSI circuit layers ofa VSI IC or component. The performance and power dissipation of planarICs is inversely proportional to the lengths of horizontalinterconnections. The VSI invention improves circuit performance byenabling VSI circuit layer die size or areal dimensions to be heldconstant or reduced in a manner that is independent of the total amountof circuitry for most embodiments of a VSI component, and thereby,improving circuit performance while increasing the amount of circuitryper VSI component or die independent of the size or areal dimensions ofthe die. This aspect of the VSI invention to hold constant or reducehorizontal interconnection lengths results in a reduction in total VSIcircuit power consumption through reduced parasitic RC effects and or areduction in the use of long interconnection signal buffers oramplifiers commonly used in planar ICs to prevent signal propagationlosses due to long interconnection lengths.

The Closely Coupled circuit layers of the VSI invention enablesperformance improvement through multiple VSI circuit layer stacking.Each VSI circuit layer corresponds with the use of current planar ICtechnology as a separately packaged planar IC mounted on a PCB [PrintedCircuit Board] or electronic circuit assembly, wherein the signalpropagation delay between these planar electronic circuits is nowtypically greater than the internal clocking rates of today's productionCMOS circuits of 1 GHz and greater. The IC signal propagation delaybetween packaged planar ICs is the result of the unavoidable lengths ofthe interconnections between these ICs, and therefore, the accompanyingparasitic RCL electronic effects which delay signal propagation. TheClosely Coupled VSI layer interconnection lengths are several hundred[100] to several thousand [1,000] times shorter than those of planar ICsarrayed on a PCB or stacked planar ICs using edge or peripheralconnection methods.

Another aspect of the VSI invention is a doubling of availablehorizontal interconnection metallization layers for each VSI circuitlayer. This is enabled through the VSI invention with the use ofmaterials that are compatible with established semiconductor fabricationmeans, and therefore, are able to withstand semiconductor metal anddielectric deposition processing techniques and temperatures. Thisincrease in horizontal interconnection routing density of the VSIinvention is enabled by thickness reduction or thinning as required ofthe backside substrate of a VSI device or circuit layer to less than 50μm and as required to less than 1 μm. The substrate may be thinned orpartially thinned before it is bonded to a VSI substrate stack, however,it is the preferred embodiment of the VSI fabrication methods that thethinning of the substrate is completed after wafer or substrate bonding.The thinning of the substrate of a VSI layer is preferably accomplishedwith use of a barrier layer in the substrate or dissimilar stackedsemiconductor materials that provide a means to precisely determine theend point for removal of the substrate. The use of a barrier layer suchas silicon dioxide of less than 500 Å and as thin as 50 Å will enable aprecision thinning of the substrate of a VSI device or circuit layer toless than 50 Å. The fabrication of horizontal interconnection on thebackside of a conventional planar circuit substrate is realized afterthe circuit wafer or device substrate is bonded to a VSI component stackor carrier substrate by one of various permanent or temporary bondingmeans, and whereupon, the backside of the device or circuit substrate ismade available for fabrication by conventional fabrication means ofelectronic or optical interconnections and completion ofinterconnections originating on the front side of the immediatelyadjacent circuit or device substrate or other circuit layers of the VSIcomponent stack.

The preferred embodiment of VSI Closely Coupled circuit layers is thethinning of one or more substrates to a thickness of less than 50 μm.Thinning of the substrate can be assisted by embedding a barrier layer,a dielectric layer or an etch stop layer beneath the active devices. Inthe case of SOI [Silicon On Insulator] substrates the buried oxide layercan be used as an etch stop for substrate thinning Nominally the barrierlayer or buried oxide layer is in a thickness range of 2,000 Å to 6,000Å which presently adds greatly to the cost of the substrate. Closelycoupled IC layers enable the buried oxide substrate layer to be lessthan 1,000 Å in thickness and preferably less than 100 Å or less than200 Å or in the range of 50 Å to 500 Å, since the buried oxide layerneed only act as an etch stop and not as in its original intendedpurpose of electrical isolation of the semiconductor device layeroverlying the oxide [dielectric] layer from the remaining semiconductorsubstrate below the dielectric layer. Once this substrate is thinnedadditional oxide or dielectric deposition can be performed to providethe circuit isolation layer that would normally be present in a standardSOI substrate. The thinner buried etch stop layer reduces device layercrystalline defects by a factor proportional to the reduced thickness ofthe buried oxide layer, crystalline defects are a common problem withcurrent SOI substrates. Further, since the purpose of the buried oxidelayer in a Closely Coupled VSI circuit layer is now to function as abarrier layer or an etch stop, it opens the opportunity to form a layerother than oxide, since the layer can be completely removed afterthinning such as an epitaxial layer. Further, the thickness of thedielectric layer can be enhanced to a thickness beyond that presentlypossible with SOI substrates to provide greater circuit isolation forbetter circuit performance.

Another aspect of the VSI invention that in addition to the fabricationof horizontal interconnections on the backside of the substrate of a VSIcircuit layer, the fabrication of circuit devices such as transistors,memory cells, resistors, capacitors, inductors is enabled. Morespecifically, the completion of circuit devices such as transistors ormemory cells partially fabricated on the front surface of the substratecan be completed from the backside of the VSI circuit layer; this isenabled by VSI bonding process and VSI precision wafer or substratethinning This specific VSI capability of completing the fabrication of acircuit device requires the thickness of the semiconductor substratewherein active circuit elements or devices are fabricated to becontrolled preferably to within a tolerance of less than 5% of thethickness of the retained substrate thickness. This is enabled by use ofa barrier layer in the VSI circuit layer beneath the top substratesurface at a depth equal to the desired thickness that the substrate isto be thinned or approximately so, compensating for additionalprocessing steps. The preferred barrier layer embodiments are silicondioxide or silicon nitride with thickness of less than 500 Å. Analternate preferred embodiment for enabling precision thinning from thebackside of a circuit layer is the use of a semiconductor substratecomposed of dissimilar materials such as SOS [Silicon on Sapphire], Sion glass or quartz, GaAs on Si or InP on Si wherein the underlyingsubstrate material such as glass or silicon can be removed byestablished semiconductor processing methods after circuit substratebonding to a VSI component circuit layer stack. The objective in theabove methods is to achieve a very well controlled thickness of theremaining portion of semiconductor substrate of the circuit layer, thesemethods allow a semiconductor layer thickness tolerance of less than 50Å to be achieved. The backside processing of the substrate of a VSIcircuit layer can also include the fabrication of a plurality of memorylayers such as those made from MRAM, PRAM, ferroelectric or dendriticmemory cells. The benefit of fabrication of memory layers on thebackside of the VSI circuit layer, in addition to the top or first sideof the VSI circuit layer, enables the opportunity for design of thememory cell density to be increased with respect to the semiconductorlogic layer associated with a less complex vertical interconnectionstructure to the memory layers, or enables double the total number ofmemory layers that can be associated with a logic circuit layer.

The Closely Coupled aspect of layers of the VSI invention enables highdensity vertical interconnections that are local to adjoining CloselyCoupled VSI circuit layers or global wherein interconnecting some numberof other VSI circuit layers of any order in the VSI component, or byforming dedicated or bused interconnections through all or group of theVSI circuit layers of a VSI component. A global bused VSI componentinterconnection structure is similar or is analogous to the well knownPCB back plane bus structure used to interconnect at right anglesdaughter PCB cards. This comparison helps to make clear theinterconnection efficiencies of the VSI vertical interconnection methodenables a connection density in excess of 1000 times greater than thestate of the art of PCB to PCB interconnection means, further, there arenone of the interconnection performance delays intrinsic to the longinterconnections of the PCBs. The VSI vertical interconnection ofelectronic substrates also includes substrates with deposited layers ofactive devices such as polycrystalline or amorphous semiconductordevices. Here the vertical interconnections fabricated between thesedeposited device layers can be extended to form interconnections toother Closely Coupled layers in a VSI component with established circuitfabrication means.

Another aspect of the VSI invention regarding backside substrateprocessing is that it permits process separation from the fabricationprocess used on the front or top side of the VSI substrate. This isenabled once a wafer or substrate is bonded on to a VSI substrate stack.The bonding process seals the top side of the substrate from effects ofmost processing steps that may be performed on the backside. If aninorganic sealing method is used such as metal thermal diffusionbonding, then the top substrate surface is hermetically sealed. Thisability to employ disparate fabrication processes on the backside of aVSI layer applies to MEMS VSI layers in addition to electronic andoptical VSI circuit layers. Fabrication processes that are not presentlycompatible or with limited compatibility such as CMOS and MRAM [MagneticRAM], chalcogenide phase change memories or dendritic memories can befabricated on the same but opposite sides of a substrate. Processes andmaterials that have unique or limited product production use would neverbe considered for integration with a state of the art high volume CMOSfabrication process line, can with the VSI invention be integrated onthe backside of the CMOS circuit with no change to the CMOS fabricationsequence or risk to its fabrication cost efficiency. Further, thin filmactive devices such as TFTs can be fabricated on the back side of aconventional CMOS circuit wherein multiple layers of thin film devicescan be fabricated with vertical interconnections not only between theselayers but also directly to the active devices on the front side of theCMOS layer.

Another aspect of the VSI invention is inclusion of optical circuitry asClosely Coupled VSI circuit or device layers. Optical circuits that arefabricated with semiconductor processing techniques on substrates suchas silicon, GaAs or quartz with dimension similar to those that would beused in the VSI fabrication process can be integrated into a VSIcomponent or IC. The same bonding means used for bonding electronicClosely Coupled layers can be used to bond optical layers to formClosely Coupled VSI layers including one or more optical circuit layers.An array of optical circuits fabricated on a substrate such as siliconarranged in much the same manner as an electronic circuit is bonded facedown [or initially face to face] onto a VSI circuit stack, the backsideof the optical circuit substrate is thinned as need and throughestablished semiconductor fabrication techniques various types ofinterconnections to the optical device and other VSI circuit layers towhich it may be bonded are fabricated on the backside and optionally abonding layer is fabricated for subsequent additions of more VSI circuitlayers. Optical circuit interconnections between VSI layers are achievedthrough such means as the coupling of adjoining wave guides on thesurfaces of VSI layers as a result of the bonding process, through themeans of reflectors fabricated onto top or backside surfaces, or throughcoupling of photo diodes and photo sensors as shown in FIG. 28 and FIG.29.

Another aspect of the VSI invention is inclusion of MEMS as CloselyCoupled VSI device layers. MEMS that are fabricated with semiconductorprocessing techniques on substrates such as silicon or quartz withdimension similar to those that would be used in the VSI fabricationprocess can be integrated into a VSI circuit or VSI component. Thebonding means used for bonding electronic or optical Closely Coupledlayers can be used to bond MEMS layers to form Closely Coupled VSIlayers including one or more MEMS device layers. An array of MEMSdevices fabricated on a substrate such as silicon arranged in much thesame manner as an electronic or optical circuit is bonded face down [orinitially face to face] onto a VSI circuit stack, the backside of theMEMS substrate is thinned as need and through established semiconductorfabrication techniques various vertical interconnections between theMEMS device and VSI circuit layers to which it may be bonded arefabricated on the backside and optionally a bonding layer is fabricatedfor subsequent addition of more VSI circuit layers. MEMS devices such asinterferometers, micro mirrors or mass storage devices benefit fromimmediate or Close Coupling to circuitry that can more accurately sensethe output of these devices or control their operations improving theirperformance as well as reducing their cost.

FIG. 28 shows a portion in cross section with VSI circuit layers 2801,2802, 2803, 2805, 2811 with optical interconnections over a MEMS layer2803 of a VSI component or IC wherein active optical laser diode 2804fabricated on the front side of single crystalline semiconductor VSIlayer 2805 emits an optical signal into a dielectric wave guide 2806incorporating optical reflectors 2807 and 2808 which is received byphotodiode sensor 2809. Also shown are TFT deposited layer andhorizontal interconnect layers 2810, digital logic circuit layer 2811and VSI layer thermal diffusion bond 2812. The optical wave guide ofFIG. 28 may also incorporate an optical wave guide coupling shown inFIG. 29 formed by the bonding of two VSI circuit layers wherein opticalwave guide 2901 on circuit layer 2903 is coupled to optical wave guide2902 fabricated on circuit layer 2904 with the formation of bond 2905and cavity 2906. The optical coupling is accomplished by an off angleend terminations 2907 off optical wave guide 2901 and 2908 of opticalwave guide 2902 wherein optical signals leaving the end of wave guide2901 are reflected off reflective metal surfaces 2909, 2910, 2911 and2912 and into the end of waver guide 2902. The cavity 2906 is vacuum orfiled with a fluid with minimum absorption characteristics for thewavelength of the optical signal.

Over the past thirty-five years the cost trend for transistors of anintegrated circuit has seen an average annual rate of reduction ofapproximately 50% resulting today in a cost of approximately 3×10⁻⁶ç pertransistor of a memory circuit and approximately 2.5×10⁻⁴ç pertransistor of a logic circuit. If this trend continues, it can beanticipated that the cost of memory circuit transistor, will furtherdecrease based on the integration progression of current manufacturingmethods to 4×10⁻⁸ç and a logic transistor to 4×10⁻⁵ç over the next fiveyears. Even though these numbers are impressive they may be at least anorder of magnitude higher than what can be achieved with the present VSIinvention.

This near “zero cost” trend of the IC transistor has resulted in greaterIC design complexity now approaching hundreds of millions of transistorsper planar IC. The advantage of this cost trend, however, is not nowbeing fully realized. IC yield, test and IC packaging are now preventingthe full realization of the transistor's cost reduction benefit. Furtherfrustrating the full realization of the transistors cost reduction isthe high cost associated with merging different IC fabrication processeson a single planar IC or the complete inability to do so.

It is an objective of the VSI invention to provide methods for fullerrealization of the present and future cost reduction trend of the ICtransistor. The VSI invention takes into account that the rapidlydeclining fabrication cost of IC transistors can offset the cost ofcircuit designs and their fabrication costs where circuit self repair orreconfigurability implemented though vertical IC integration methods areused as means to achieve increased IC yields, lower packaging costsincluding reduction of net system assembly costs and the merger ofdisparate incompatible semiconductor fabrication processes andtechnologies. The VSI invention achieves this result by enabling agreater density of IC integration than is possible by the foreseeablemeans available to planar IC fabrication through the implementation ofvertical integration and fine-grain vertical interconnections aligned toless than 2 μm pitch and the thinning of the semiconductor substrate toless than 1,000 Å or to any dimension as required. VSI wafer orsubstrate thinning enables fabrication processes to be performed on thebackside or underside of circuit layers providing the opportunity fornovel transistor design improvements and fabrication of additionalconventional [horizontal] interconnections with equivalent circuitcomplexity and density presently only afforded with the topside of theintegrated circuit.

The VSI invention enables the cost effective trade-off of the use ofdynamic or static field programmable circuitry to implement circuit selfrepair with the use of spare or redundant circuitry. The implementationof these methods through the VSI invention improves IC yield, reducesthe circuit design complexity and the merging of technologies andprocesses through modular IC structures with higher degrees of assuredoperation.

The VSI fine grain vertical interconnections preferably are formed atthe time two circuit wafers or substrates are bonded [preferably bythermal diffusion bonding] and during the backside interconnectionfabrication of one subsequently thinned wafer or substrate so that thethinned substrate is less than 50 μm and preferably less than 5 μm. Inthe case where the substrate being thinned is an SOI substrate, all ofthe silicon is removed up to the buried insulation layer [the buriedinsulation layer is typically oxide but alternate insulation materialscan be used such as nitrogen to form a nitride layer] underlying thesemiconductor device layer.

The VSI invention is a set of circuit and MEMS integration methodsenabling the fabrication of electronic systems or subsystems as one ICdie or VSI component instead of what are now and for the foreseeablefuture assemblies of large numbers of individually packaged planar ICs.The integration methods of the VSI invention result in greater ICintegration than that possible with conventional planar IC integrationand with IC benefits of higher performance and net lower manufacturingcost and power dissipation than an equivalent non-integrated set ofplanar ICs. VSI closely coupled IC circuits enable the performancelimiting off-circuit or off-chip interconnections or I/Os ofconventional planar ICs to be replaced by their integration into the VSIIC as vertical interconnections between VSI circuit layers or morespecifically the interconnection density between the ICs of VSI IClayers.

The VSI invention enables novel methods addressing present ICfabrication limitations of yield enhancement, performance enhancement,cost reduction, lower power dissipation, NRE cost reduction, and designand fabrication complexity. The VSI invention reduces the requirementfor use of second-tier IC interconnect means such as IC carriers orpackages, IC carrier sockets, PCBs and PCB edge connectors. Theintegration of second-tier interconnect means results in reduced costand increased circuit performance, but also total circuit power, sizeand I/O reductions in a range of 100× to 10,000×. Further the VSIinvention is a means that simplifies the design, development, maskmaking, final test and burn-in of ICs. The IC integration progressionhas also provided the infrastructure and means for implementing the VSIinvention.

The solid solubility or diffusion of one metal into another metal of ahigher melting temperature is a means for forming a VSI circuit layerbond at a lower temperature and resulting in an alloyed metal at thebond interface of the bonding layers with a higher working and meltingtemperature. Metal films or layers deposited on the VSI circuit wafersor substrates for the purpose of forming bonds of VSI circuit layers aredeposited with semiconductor techniques such as sputtering, evaporationor CVD [Chemical Vapor Deposition]. Such films made from In, Sn, Zn, Cdor Ag or alloys of such metals when deposited on top of another metalfilm with a higher working or melting temperature such as Cu, Al, Ni orPd will with appropriate annealing temperatures diffuse into each otherforming an alloy of high working temperature. If the lower workingtemperature film is thinner relative to the higher working temperaturefilm, the resulting alloy film will have a higher working temperaturethan if they were in equal proportions.

The VSI invention uses this physical relationship of metal films to usea first wafer or substrate bonding temperature that is lower than thefinal working temperature of the VSI circuit layer bond. This is done byusing a lower melting temperature metal such as Sn over a film of Cu onthe two bond contact surfaces of VSI circuit substrates to be bonded.For example, with a first Sn film of 500 Å and a second underlying filmof Cu film of 5,000 Å to 7,500 Å, applying temperature of 180° C. andpressure of 2 atmospheres will bond the Sn first films, and withsubsequent temperature annealing steps of 180° C. or higher, the Sn willdiffuse into the Cu layer creating a SnCu diffused or alloyed film atthe bond interface with a higher working temperature than the meltingpoint of Sn. Bonding films made of two or more deposited metal filmswill be herein referred to as Diffusion Alloy bond layers. This type ofmetal bond layer is novel in its use in integrated circuits and MEMS andcan be used in VSI fabrication to lower the bonding temperatures of VSIsubstrates.

Another example of dual metal thin film diffusion bonding is the sputterdeposition of a 50 Å to 500 Å film of Sn [tin] over Al [aluminum]. Thedeposition of the Sn should be done after the removal of the approximate35 Å thick Al oxide on the surface of the Al film by a method such assputter etching or the Sn film should be deposited following thedeposition of the Al film without exposure of the Al film to atmosphereor oxygen, and therefore, avoiding the formation of the Al oxide film onthe Al film; the Sn film can be deposited over the Al film to preventthe formation of Al oxide on the Al film. When two substrates or waferswith the SnAl metal film stack depositions are diffusion bonded, the Snfilms enable a bond between the substrates to be rapidly formed.Subsequent thermal annealing of the bonded substrates will cause thethin Sn film to diffuse in to the thicker Al film. The benefit of thisbond processing sequence is to simplify and to accelerate the bonding ofAl films and to create an alloy of SnAl at the diffusion bond interfacethat has a higher melting temperature than Sn such that the workingtemperature of the IC stack is higher than the melting temperature ofSn. Another example of such a metal sequence is Sn/Cu/Al. In thisexample the Sn layer may serve as an etch mask for the Cu/Al films andthe Cu film will act to prevent the formation of an SnAl diffusionintermetallic alloy. The characteristics of the diffusion formedintermetallic alloys are determined by the thickness of the variousmetal films of the film stack and their exposure sequences totemperature in terms of duration and temperature range. The thinner theprimary bonding metal film is, the greater the control available inreducing the emergence of an undesirable intermetallic diffusion alloy.

The VSI invention is a Closely Coupled stacked integrated circuitfabrication technology. The primary benefit of Closely Coupled circuitstacking integration is its ability to achieve electronic circuitcharacteristics equivalent to that of planar circuit integration fromthe stacking of a plurality of individual planar ICs. Closely coupledintegrated IC layers have the same electronic and electrical operationas a planar integrated ICs. However, there are clear benefits thatClosely Coupled integration provides that planar integration does not.These are shorter wire lengths from fine grain vertical interconnectionsand smaller die size, the capability to arbitrarily integrate widelydissimilar semiconductor device fabrication processes [digital CMOS,DRAM, Flash, etc.] or technologies [SiGe, SOI, GaAs, SiC, GaN, etc.] asseparate circuit layers, and the capability to increase wiring densitythrough the application of very dense vertical interconnections, therebyreplacing equivalent horizontal cross die interconnects or localinterconnections among devices of immediate proximity on separatecircuit layers.

The VSI invention through Closely Coupled circuit fabrication enablesone or more of the following:

-   -   1. Fine grain vertical system bus or buses, ranging in data        width from a typical 16 or 32 wide data width to several        thousand data bus lines.    -   2. Reduced I/O [off chip] contact count versus the total count        of I/O contacts of a planar circuit equivalent chip set.    -   3. Fine grain vertical interconnections for enabling or        disabling whole circuit layers or portions of circuit layers.    -   4. Fine grain vertically interconnected redundant or spare        circuit layers or portions of circuit layers.    -   5. Inventory or generic multiple application use IP circuit        layers.    -   6. Fine grain vertically interconnected FPGA, CPLD or PLD        circuit layers    -   7. No tooling IC integration.    -   8. Fine grain vertically interconnected yield enhancement logic        comprising a whole circuit layer or portion of a circuit layer.    -   9. Fine grain vertically interconnected MEMS layer or layers        such as antennas, SAWs [Surface Acoustic Wave], circuit probe,        magnetic disk head or video image sensors.    -   10. Fine grain vertically interconnected memory subsystems of        such memory technologies as DRAM, Flash, EEPROM, SRAM, CAM,        PRAM, dendritic, Ferroelectric or Ferromagnetic.    -   11. Circuit layers of different semiconductor technologies such        as GaAs, CMOS, SOI, InP, GaN or GeSi, or passive circuit layers        made of such passive circuit devices as resistors, capacitors or        inductors.    -   12. Fine grain vertical interconnections used to implement        circuit defect repair with fuses and or anti-fuses during        burn-in processing.    -   13. Horizontal interconnect fabrication on the backside of        thinned circuit layers allowing the horizontal interconnect        density to approximately double.

The primary benefit sought from the use of planar ASICs is to achievehigh performance of an application by fabricating selected portions ofthe application as hardware functions. This narrow focus to achieveperformance utilization of an application is also the most seriouslimitation to the use of ASICs for the reason that once hardwarefunctions or IP [Intellectual Property] is committed to a hardwaredesign in a planar IC its reuse in another IC will require at leastpartial redesign of the circuitry to place it into the circuitry of asecond IC, the cost of fabrication tooling masks and physical testingverification. Perhaps the most important limitation facing present ASICsbeing made with CMOS technologies of 150 nm and smaller fabricationprocesses is their increasing costs due to mask tooling and achievingcost economies for these circuit manufacturing processes demands largeproduction volumes. The great majority of ASICs designs are intendedonly for low production volumes which significantly increases theircosts.

It is an objective of the VSI invention to reduce the cost of ASICs orsmall volume production circuits by increasing their utilization as aVSI circuit layer or portion thereof which allows the reuse of the IP ofthe ASIC in a second application without design changes, additionalfabrication tooling, production or separate physical testing. Largeproduction lots of an IP as a separate VSI circuit layer could be madewith the expectation of higher application utilization. Unlike completedor fabricated planar ICs, the VSI circuit wafers or substrates can bethought of as reusable circuitry from the stand point that theirsubsequent integration is possible on an as is basis into alternate VSIcircuit applications, and without losing the well known attendantbenefits of planar IC integration. Subsequent VSI IC or component designchanges by changes to one circuit layer or the addition of circuitlayers does not unavoidably result in making the existing VSI layersobsolete or require the remaking of mask tooling for the existing VSIcircuit layers as is required when changes are made to planar ICs.Furthermore, VSI component density can be increased or decreased withoutcircuit redesign; the addition or removal of VSI circuit layers issimilar in principle to the addition or removal of daughter PCBs from amother board or back plane. Furthermore, any and all subsequent circuitdesign changes or additions to an existing circuit layer only requiresthe remaking of that specific VSI circuit layer. This is a clear andsignificant novel advantage over planar ICs in terms of IC development,manufacturing and management of fabricated IC inventory.

The IC integration progression to ever smaller circuit feature sizes[lithographic] has enabled the manufacture of 32-bit and 64-bitmicroprocessors on a single semiconductor chip, and most recently two64-bit microprocessors on a single semiconductor chip. Integrated withthese microprocessors also is some amount of volatile memory such asSRAM or DRAM, this on chip memory is extremely important to theperformance of the microprocessor. This integration progression is alsotrue for other circuit types such as PLDs [Programmable Logic Devices],also referred to as FPGA or CPLD circuits, network processors, graphicprocessors, ASICs [Application Specific Integrated Circuits] and ASSPs[Application Specific Standard Products], to name some broad class ofcircuit types. The integration progression is valid for MEMS[MicroElectro-Mechanical Systems], a new circuit type with need tointegrate sensor and mechanical functions with electronic or opticalcircuitry, whereby it can be expected that MEMS will eventuallyintegrate circuitry such as microprocessor, memory and wirelesscommunications.

The IC integration progression is expected to continue with theintegration of microprocessor circuits with ever more memory andprocessor related control circuitry such as graphic processing logic andDSPs. This progression is driven by the demands for more performance andlower cost, and with portable electronic devices lower power and smallerphysical form factor or finished circuit size. The result of reducingcircuit feature sizes is increased circuit operating performance, lowercost, lower power and smaller form factor or size per some unit ofcircuit area. This is well know to those skilled in the art.

The terminology used to describe ICs is diverse. More often than not thenames of existing IC terminology owe their origins to efforts to givethese IC products a meaningful description for the times of theavailable market and technology, but the integration progressionrelentlessly continues to render less useful such original meaningfuldescription. IC names such as microprocessor, DRAM, DSP and PLD arebecoming less useful because the integration progression has enabledthem to be combined into one planar IC, and new names like MEMS willmost certainly experience similar declining usefulness. It is because ofthis history that the new and very general term SoC [System on Chip] hascome to be used. There are two other very familiar terms, ASIC[Application Specific IC] and ASSP [Application Specific StandardProduct] which were coined to describe a class of custom designed ICs orICs designed for a specific application and used depending upon whetheran IC was intended for a narrowly defined use [ASIC] or a broader andmore general but specific market use [ASSP]. It can be argued that allICs have always been and always will be custom ASICs, since all ICs aremade for some narrow or broad set of applications. The use of the termASIC in this description when in reference to the VSI invention herein,is meant to apply broadly and to refer to all semiconductor fabricatedcircuitry and devices of which only a partial list includesmicroprocessors, graphic processors, network processors, PLDs, FPGAs,CPLDs, DRAM, Flash, MEMS, sensors, photosensor arrays, CCDs, basebandprocessors, CAMs, configurable and reconfigureable circuits, passivecircuit arrays, analog circuits, hybrid circuits and mixed signalcircuits.

The clear end objective for most electronic products or applicationscomposed of multiple ICs is to integrate the ICs into a single chipsolution referred to by the all encompassing term of SoC [System onChip]. The limits of circuit integration are feature size, lithographicstepper reticle size [maximum lithographic image size] and yield. Atthis point in time feature size is approaching 0.12 μm, stepper reticlesize is approximately 25 mm by 30 mm and circuit yield is inverselyproportional to the size of the semiconductor circuit die with bestcircuit yields obtained with chip sizes of less than 1 cm². And ICs arealso made from different semiconductor manufacturing processes andtechnologies, such CMOS, flash, DRAM, BiCMOS, GaAs, GaN, InP, etc.Processes like CMOS and DRAM are difficult and expensive to integrate,semiconductor technologies such as GaAs, GaN or InP have proven to beextremely difficult or impossible to date to commercially integrate withsilicon as a single SoC planar circuit. Larger electronic systems suchas multi-processors computer systems, Storage Area Networks and internetrouters are performance limit by the methods used to interconnect thevarious highly integrated ASICs, μPs and memory circuits from which theyare made. In such systems the on-chip IC clock speed can be as much ormore than several times higher than the clocking speed used tocommunicated between ICs. The inter-IC wiring interconnect consisting ofIC package, IC socket, PCB, PCB connectors and back plane are thecontributors of the single greatest delay in electronic systemperformance. Greater integration of the components of such systems isexpected, however, single chip integration of large electronic systemsis not soon expected, and therefore, electronic systems as presentlyassembled will continue to have performance limitations due to theinterconnections between IC components. It is an objective of the VSIinvention to provide fabrication means to enable the integration ofmixed IC semiconductor processes and technologies, and to reduce theinterconnection delays attributed to ICs in electronic andelectro-optical system and subsystems.

The VSI vertical interconnections enable a circuit to be reconfigureableby function with similar facilities as it uses in configuring a circuitto delete or add circuitry as a result of a circuit defect. The benefitof VSI vertical interconnections for the implementation ofreconfigureable circuits such as PLDs, FPGAs or CPLDs is reducedinterconnect routing complexity and or a reduction in the number ofhorizontal interconnection layers per VSI circuit layer, these benefitsresult from the use of smaller die dimensions and the segregation toseparate VSI circuit layers of various logic circuitry and memorycircuitry. An example is global routing for FPGA type circuits where diesize can be as large as 600 mm² with global horizontal interconnectionsas long as 20-30 mm. The use of VSI vertical interconnections can reducemaximum global horizontal interconnect lengths to less than 2 mm with amajority of the FPGA logic blocks globally interconnected by lengths ofless than 100-200 μm. This is done by segregating or partitioning theFPGA or CPLD circuit into a set of circuit layers with a die area of25-30 mm². The VSI partitioning of a planar FPGA circuit into a set ofVSI FPGA circuit layers allows the majority of FPGA circuit blocks to beinterconnected vertically and reduces the average interconnection lengthto a function of the die thickness, a length of nominally less than 200μm, and the maximum interconnection length to a function of the diesize, a length of nominally less than 10 mm.

Planar PLD, FPGA or CPLD circuits provide an unrivaled flexibility toachieve hardware development and performance efficiencies through animplementation of a logic function by the programming means of the FPGAcircuit. This benefit, however, is significantly offset by a low densityof programmable interconnections of and between logic functions, lowgate density and low memory density relative to custom logic circuits[ASICs] which results in higher FPGA circuit cost. FPGA circuits arepresently limited in the number of gates per circuit by the field sizeof the lithography tool or reticle and the global routing resourcesnecessary for transmission of data signals across the circuit. PLDrouting resources typically require 60 to 70% of the area of a PLDcircuit. Dynamically reconfigurable PLD circuits or PLD circuits thatcan be reprogrammed during operation are limited by the availabilityrouting resources. The VSI invention significantly reduces the cost ofplanar FPGA circuits by increasing the interconnect, gate and memorydensity. However, the VSI invention further uniquely improves on thecapability and capacity of present FPGA circuits by enabling an increasegate and memory density beyond current planar circuit limitation due tolithography, and to incorporate dedicated circuit functions or IP on anas needed basis without requiring design change to a VSI FPGA circuitlayout by implementing hardwired or dedicated circuit functions or IP onVSI circuit layers that can be added to a VSI FPGA component.

The lithography die size limitation is a physical constraint on thefabrication of all planar ICs, and therefore, limiting the amount ofcircuitry that can be integrated on any single planar IC regardless ofwhat planar fabrication process used. The amount of circuitry that canbe integrated into a VSI IC is not limited by the lithographyfabrication limitation on die size, but by the integration of aplurality of circuit layers providing the integration efficiencies of atleast that of planar integration.

A unique advantage of the VSI fabrication method of making stackedcircuits with SOI substrates fabricated with the SIMOX process is thatthe buried insulation layer or barrier layer of the SOI substrate needonly be as thick as that required to complete the removal of theunderlying substrate. The thickness of the buried insulation layer canbe as thin as 50 Å to 150 Å versus typical SOI buried insulator layer of4,000 Å. The direct advantage of such a thin buried insulation layer isthat there is less crystal lattice damage of the overlying semiconductorlayer during the implant of the insulating atomic species. Once theunderlying substrate is completely removed the insulation layer isexposed and the thickness of the insulation layer can be enhanced bydeposition of insulation films.

The VSI invention integration method uses the fabrication of verticalinterconnects on less than 4 μm pitch and with the wafer to waferalignment and bonding methods provided herein, the fabrication ofvertical interconnects of less than 250 nm [0.25 μm] pitch and less than100 nm [0.1 μm] pitch. A 4 μm pitch enables a vertical interconnectdensity of 62,500/mm², and a 100 nm [0.1 μm] pitch enables a verticalinterconnect density 100,000,000/mm². Vertical interconnect pitch withgeometries of less than 1,000 nm [1 μm] pitch are necessary in order tomatch the integration scale of a majority of current circuit devices.This density of vertical interconnections between VSI circuit layerseliminates a majority of interconnection restrictions that presentlyexist between planar circuits and result in performance limitations oninter IC bandwidth often referred to as I/O bottlenecks. Present planarICs have external [off-chip or off-die] I/Os of less than 500connections and are limited to a maximum I/O count of approximately4,000; the maximum I/O count limitation results from packagingtechnology constraints in addition to cost constraints. The VSI highdensity fine grain vertical interconnections can be organized intostandardized placements in the layouts of a family or library of circuitlayers with the objective of enabling the subsequent direct coupling ofthese interconnections to overlying [underlying] circuit layers of a VSIIC. Further, with a large number of vertical interconnections perplacement, some number of these interconnections can be spare or unusedinterconnections and available for use in a future VSI IC design. FIG.2c shows a standardized placement of several fine grain verticalinterconnection blocks 201 c, 202 c, 203 c and within such blocks thevertical interconnection density may vary independently by pitch inaddition to the total number of interconnections per block; for example,block 201 c may have 1,000 vertical interconnections arrayed with a1,000 nm [1 μm] pitch for providing power between circuit layers, block202 c may have 15,000 vertical interconnection arrayed with a mix on twoor more pitches from 2,000 nm to 1,000 nm, and block 203 c may have80,000 vertical interconnections arrayed with a 200 nm pitch toimplement a high bandwidth bus connections.

A primary objective of the VSI invention is the reduction of theinterconnect length of and circuitry associated with off die or externalIC circuit interconnections commonly referred to as IC I/O bond pads orI/O connections 11 as shown in FIG. 3. External IC interconnectionstypically account for more than 50% of the power dissipation of an IC.In the case of a 64 bit DRAM IC, the I/O circuitry necessary to sendsignals on and off the DRAM circuit account for approximately 90% of thepower dissipation. The direct benefits of reducing the number ofexternal I/Os of an interconnected set of ICs in addition to lower powerdissipation are smaller die size and an increase in the combinedperformance of the set or network of interconnected ICs. The benefit ofreduced power dissipation of the VSI invention follows from thereduction of inter IC or circuit layer connection wire lengths totypically less than 200 μm implemented with fine grain verticalinterconnections, therefore, reducing or eliminating the I/O circuitryand associated power needed to drive circuit signals lengths of severalinches to tens of inches. The benefit of reduced die size in VSIinvention follows from the reduced foot print of a fine grain verticalconnection that can be 2,500 to 10,000 times smaller than an I/O bondpad 11, therefore freeing the surface area that would be required of aplanar IC. This VSI benefit is most significant with ICs that requireadditional surface area beyond that necessary for the implementation ofcircuitry in order to provide area for bond pads are referred to as bondpad limited. The benefits of higher performance in VSI circuit layersfollows from the shorter inter IC connection lengths. The VSI verticalintegration method enables the elimination of external I/O circuitdrivers and pads between circuit layers by routing theseinterconnections to one or more of fine grain vertical interconnectionsor vertical buses. The fine grain vertical interconnections can bedesigned to implement any order of connections between each circuitlayer of a VSI IC through fabrication of interconnection routing on thebackside of a circuit layer, therefore, at a minimum any routingconnection network between a set of planar ICs can be reproduced whensuch ICs are stacked in a VSI IC or component.

The VSI integration enables the design of a circuit to be the determinerof VSI circuit layer foot print or die size and not the total amount ofcircuitry comprising the IC as in planar ICs. The performance and yieldof a planar circuit is directly related to its die size. The performanceof planar circuits made with fabrication geometries of 0.15 μm and lessare dominated by the propagation delay of the wire length used tointerconnect the transistors and not the switching propagation delay ofthe transistor. The design of a VSI circuit enables the arbitrarypartitioning or placement of circuit functions per circuit layer andcombining horizontal interconnections with fine grain verticalinterconnections between circuit layers, therefore, the VSI circuitlayer foot print or die size is a circuit design decision.

The VSI integration reduces circuit power dissipation and increasescircuit performance through smaller die size and the elimination ofstacked IC to IC I/O drivers with fine grain vertical interconnection.Circuit integration with geometries below 0.15 μm dramatically increasesthe density of active devices per unit area of semiconductor substrate.However, as geometries are reduced, circuit operating voltages are alsoreduced, reducing the transistor signal drive capability andnecessitating greater numbers of repeater circuits in order to send asignal across the surface of the IC of lengths of several thousandmicrons [4-20 mm] or more. This in turn increases the power dissipationof the circuit. The fine grain vertical interconnections of a VSIcircuit layer nominally vary in length from a few microns to 10 μm percircuit layer with total vertical wire lengths through the complete VSIIC or component of nominally less than 150 μm, although physicalimplementation of vertical wire lengths of greater than 1,000 μm [1 mm]are possible, a practical design driven maximum length of less than 600μm [0.6 mm] is anticipated. The shorter VSI vertical wire lengths wouldreplace all global or long wire lengths of an equivalent planar circuitreducing the wire propagation delay nominally by more than a factor of10 and power dissipation by a design dependent amount.

Secondly, IC to IC I/O drivers often account for the majority of powerdissipation of a planar circuit and the number of I/Os of a planarcircuit design may be restricted in order to reduce total powerdissipation. The power dissipation of off chip I/O drivers results fromthe resistance and capacitance loading of the interconnections betweenplanar circuits consisting of at least circuit packages and PCBs[Printed Circuit Boards], but may further include package sockets, PCBedge connectors and back planes. These same interconnections are theprimary determiners of net electronic system performance [exclusive ofdelays attributed to electro-mechanical sub-systems such as disk drives]for most electronic systems such as PCs, servers, network processors orsupercomputers. The use of fine grain vertical interconnect in VSIcomponents eliminates the need for conventional I/O drivers betweencircuit layers due to the shorter vertical path length between all VSIcircuit layers, and this same shorter vertical path length betweencircuit layers eliminates the performance delay normally resulting frominterconnections between planar ICs.

The VSI invention enables simplified methods for high speed electronicand or very wide data path transfer of information between two or moreVSI circuit layers. High speed transfers of information between planarICs at rates of greater than 500 Mbps per single interconnection requirecustom transceiver logic specific to this function. The Rambustransmission technology is a very well known example of such transceiverlogic. The short connection [wire] lengths provided by fine grainvertical interconnections of the VSI invention enable information to betransferred from one circuit [IC] layer to any other circuit layer ofthe same circuit stack with no more circuitry than would be required fortransmission over the surface of a planar circuit. It also follows fromthe use of fine grain vertical interconnections that its capability forinterconnection densities of less than 2 μm pitch enables making ofarbitrarily wide data paths between circuit [IC] layers within a VSIcomponent. Such data paths can be of any practical width such as 1,000to 4,000 connections, but connection widths of 10,000 or more can beimplemented without restriction within a VSI component.

The VSI invention enables a new method for built-in self test of a VSIIC with a standardized or specialized tester capability comparable tothat now provided by ATE systems. This is accomplished by incorporatingtester logic on a separate circuit layer or portion of a circuit layer.The tester circuitry uses fine grain vertical interconnections as directconnections or as standardized bus structures to send test signals toother circuit layers. In the preferred embodiment the tester circuitryis available as a standardized circuit layer that can be programmed totest all or most of the various circuit layers through standardized orcommon busing means that test a circuit layer as a whole or portionsthere of. The tester circuit layer may also be fully redundant toenhance the probability that tester circuitry will be available toperform testing. Secondly, there may be more than one type of testerlogic incorporated on one or more circuit layers depending on the typesof circuit layers in the VSI circuit stack or component. This approachwhere a general purpose or broad application built-in circuit tester isincorporated as a circuit layer of a VSI component avoids the obviousand considerable design impact that would result if the tester logicwere to be incorporated as part of a planar circuit. The availability ofthe high density VSI fine grain vertical interconnections allow testerconnections on any specific circuit layer to be implemented through astandardized test interface protocol with routing to standardizedvertical bus interconnection placements on all circuit layers. It isalso in accordance with this aspect of the VSI invention that thismethod of built-in self test would eliminate the need for VSI IC testingby current ATE systems and allow all or the majority of VSI IC testingprocedures to be performed during IC burn-in processing, therebyreducing the cost of VSI IC testing and the present complexity ofburn-in tester circuitry, since no additional burn-in test circuitry ortester programming would be required as presently required for planarcircuit burn-in. The cost benefit of the VSI method of built-in circuitself test increases as the number of circuit layers are increased fromthe stand point of higher tester logic utilization and lower testerlogic cost as a percentage of total circuit layer cost. An additionaladvantage of this method of built-in self test is that it gives thecircuit the option of using this internal tester logic capability tovalidate the integrity of the complete circuit or portions thereofduring the useful life of the circuit. Further, this method enables theVSI component to provide stand-by [stand alone] or dynamic self testing,or a means to perform circuit operational monitoring to observe circuitdegradation over its useful life. The availability of ATE orprogrammable generic or specialized tester logic also enables internalVSI IC defect detection and reconfiguration when in combination withreconfiguration circuitry and or sparing circuitry.

VSI integration reduces the need for circuit packaging and provides ahermetically self-sealed package. Only one conventional package may berequired per VSI component, this reduces the number of packages thatwould have been required for the VSI IC's equivalent as multiple planarcircuits to one or none. Reducing the number of packages in anelectronic assembly increases circuit yield in addition to a reductionin circuit component cost; the IC packaging process has a nominal 1% orgreater yield loss. Further, the VSI IC can form its own package or isself packaging. This results from the VSI bonding process where the topsurface of a completed VSI is the backside of the last circuit layerbonded onto the VSI component. This means all electronic device surfacesare interior to the VSI circuit layer stack and protected from damage.This also allows I/O bond pads to be placed anywhere on the VSI topsurface without concern of damage to circuitry underlying that may bedirectly under a bond pad. When a VSI IC is fabricated with thepreferred bonding method of thermal diffusion bonding with inorganicbond materials, a hermetic seal at the edge of all circuit layersprevents moisture or chemical vapor contact with the electronic surfacesof the circuit layers.

The IC integration progression below 0.15 μm [150 nm] reduces the sizeof the IP or circuit foot print but not necessarily the die size of aplanar IC because the size and number of I/O [off chip] contacts or bondpads are not affected. This is a frequently occurring condition wherethe size of a die is said to be bond pad limited, meaning that the sizeof the die is not reduced proportionately with the reduction of areaoccupied by the circuitry on the die when fabricated with smallergeometries. The integration of additional off chip circuitry or IP in aneffort to reduce I/O count is most often limited by the size of off chipIP that would be included, the inclusion of the IP often increases thenet I/O count or makes the circuit design non-manufacturable, or the IPis unavailable except as a separate planar circuit. The VSI inventionavoids bond pad limitations because the fine grain verticalinterconnections pads are nominally more than 2,000 times smaller thanconventional planar IC bond pads. Further, prefabricated IP can beintegrated into the VSI component without requiring circuit redesign andthere is no practical limit to the amount of off chip circuitry or IPthat can be added as separate VSI circuit layers. This aspect of theinvention enables the VSI component to achieve an I/O bond pad countthat is significantly less than the bond pad count of equivalent planarcircuit.

An example of VSI component bond pad reduction is given by taking a setof planar ICs comprising a microprocessor, DSP, one or more ASICs, CPLDsor FPGAs, several SRAMs and CAMs, and some number ofSerializerDeserializer circuits which would be mounted andinterconnected via a PCB and with less than 200 contact edge connectionson the PCB. Fabricating these planar ICs with perhaps a total of as manyas 3,000 I/O bond pad connections as VSI circuit layers of a VSIcomponent would result in a single circuit die with approximately 200 ofI/O bond pads corresponding to the edge connections required by the PCBupon which the stacked circuit would be mounted, or approximately a morethan 10 to 1 reduction in bond pads.

In accordance with the invention it also enables a reduction in thedesign complexity and numbers of metal horizontal interconnection layersthan may be required of a planar IC. The reduction of IC geometryincreases the number of transistors that can be fabricated to make aplanar IC also increases the wiring complexity and number of wiringlayers needed to effect the connections of structures of transistorswhich take the form of microprocessors, DSPs, memory arrays, registerarrays, and IPs of various functions. The continuing integration of moreof these circuit structures results in increased circuit design andplacement complexity and additional metal horizontal interconnectionlayers in planar ICs due to the requirement to complete the high numbersof interconnections between the circuit structures and or IP over thesurface of the IC. Secondly, the placement of circuit structures isunique to each circuit design causing a repetition of design effort foreach planar IC. It is clear that the design complexity of theseinterconnections layers and the need for additional interconnections arelimited today by the number of physical horizontal interconnectionlayers that can be fabricated. The VSI invention enables thepartitioning of the circuit structures of a planar IC to separatecircuit layers and a reduction in the number of required horizontalmetal interconnection layers with fine grain vertical interconnections.This aspect of the VSI invention has the direct benefits of reduced diesize, reduced design complexity from the reduced number of circuitstructures per circuit layer and through standardized placement of finegrain vertical interconnections per circuit layer, reduced horizontalinterconnection layers per circuit layer due to fewer circuit structuresin combination with the use of vertical interconnections, and higherperformance through shorter interconnection lengths between circuitstructures.

The VSI invention uniquely enables SoC circuitry through the following:

-   -   1. The use of different semiconductor processes or technologies        per circuit layer.    -   2. Design control of die size    -   3. Reduced I/O bond pad count through fine grain vertical        interconnections.    -   4. The use of passive circuitry as one or more circuit layers.    -   5. The use of MEMS.

One of the objectives of the VSI invention is to enable an increase ofinformation transfer between memory and logic [ASICs, μPs, graphicsprocessors] circuits in both of the fundamental measures of databandwidth: data line transfer rate and data path width. This disclosurewill describe novel methods of making and device implementations forintegrating the IC interconnect components of IC sockets, PCBs, PCBconnectors and back plane onto stacked logic and memory chips.

In accordance with the invention, closely coupled stacked ICs or VSIcomponents are formed of circuit layers or planar circuits where eachcircuit layer can be made from an arbitrary and unrestricted choice ofcircuit device fabrication technology and process to implement active orpassive circuit elements or devices. The circuit layers of a VSIcomponent are circuits of 50 μm thickness or less, typically less than20 μm or as thin as 2 μm, and composed of the layout of single circuitelements or devices or the groupings of various single type circuitelements as Circuit Blocks interconnected by conventional horizontalinterconnect means and further connected as required by fine grainvertical interconnections which can be scaled or implemented todimensions compatible with the horizontal interconnection means used inthe fabrication of the individual circuit layers. A VSI IC can beimplemented solely with a combination of fine grain verticalinterconnections between the various circuit elements or Circuit Blockson the various circuit layers of VSI component. The VSI componentpreferred embodiment is implemented with one of several possible yieldmanagement methods in combination with fine grain verticalinterconnections.

Another aspect of the VSI invention is a method of making memorycircuits of widely varying capacity with a predictable yield of greater95%, resulting in a lower cost per bit than planar memory ICs and withthe capability to use customized control logic in the VSI memorycomponent but still achieve the cost benefit normally attributed only tothe very high production volumes of fixed memory design circuits such asDRAMs or flash. This aspect of the VSI invention includesimplementations not limited to flash, DRAM but also includes SRAM, MRAM,PRAM [Phase-change RAM], dendritic, GMR or other such memory cells.

The width and transmission rate of an off-chip bus determinestransmission bandwidth for moving information within a planar IC. Buswidths for conventional planar circuits vary in a range up to 256 signallines which are intended to match the processor data width or the widthof the off-chip cache or memory associated with the processor. Theability of a processor to move information from one memory area toanother, to or from large memory I/O buffers associated with I/Oprocessing logic, context state changes of several thousand bytes or themovement of large messages in a communications router are examples ofwhen throughput performance of an IC would be limited by a bus width of256 or even 512 signal lines. Off-chip connections or I/Os for presentplanar ICs are limited to less than approximately 2,000 by horizontalinterconnect layer density, packaging and power dissipation. VSIfabrication methods enables multiple vertical interconnect off-chipbuses of several thousand signal lines each, with a capability of totaloff-circuit layer I/Os exceeding 100,000, and no more increased powerdissipation than if such a bus were an on-chip transmission bus.

The methods of the VSI invention enables the fabrication of a new classof single die ICs which includes without process integrationrestrictions digital logic, most types of memory, mixed signalcircuitry, sensors, passives, and any other type of semiconductor basedcircuitry and MEMS. The VSI methods are generic in design andfabrication allowing new applications to reach lower manufacturing costlevels without the normally attendant requirement of mass volumeproduction rates.

Another aspect of the VSI invention is the ability to reduce the numberof horizontal interconnection layers of an IC layer and or the routingcomplexity of the horizontal interconnect layers for the implementationof large numbers logic function units and or for the implementation ofspare logic circuitry for circuit repair in the event of manufacturingdefects or operating life-time circuit failures by arranging the designof logic functions vertically and interconnecting them with fine grainvertical interconnections. Vertical interconnections used in this mannercan substitute for horizontal interconnections and allow for much higherlevels of interconnection density due to the fine pitch [less than 1μm], and therefore, small cross-sectional area of the verticalinterconnections, the implementation of which is not related to orrestricted by the number of horizontal interconnection layers of acircuit layer.

The VSI component or IC can be implemented with internal or externalyield management circuitry specific to the layers of a VSI IC but notnecessarily used or required for use with all circuit layers or all subportions of any circuit layer. The VSI IC contains one or more circuitlayers with yield management circuitry for specific use with one or morecircuit layers of a VSI IC and connected to those circuit layers withfine grain vertical interconnections, and or a combination of fine grainvertical interconnections some of which are common to each circuit layerand unique to each circuit layer of all or a subset of the circuitlayers of a VSI IC for implementing an external connection for access toyield management circuitry. The VSI IC can be implemented with acombination of fine grain vertical interconnections some of which arecommon to each circuit layer and unique to each circuit layer to enableor disable individual circuit elements, Circuit Blocks, variousgroupings of same or whole circuit layers through voltage supplyconnections.

Additionally, in accordance with the VSI invention, the fine grainvertical interconnections are used to make connections that test,permanently or temporarily program, configure, reconfigure, repair,dynamically reconfigure, dynamically enable or disable, and powerindividual or groups of circuit elements or Circuit Blocks of a circuitlayer or whole circuit layers from one or more controller circuits on aseparate circuit layer or layers internal to a VSI IC, external to a VSIIC or a combination of both. The VSI fine grain verticalinterconnections are further used as a means to establish customizedconnections between circuit elements and Circuit Blocks on differentcircuit layers. The VSI fine grain vertical interconnections are furtherused as a means to establish standardized physical circuit layoutplacement of inter circuit layer I/O contacts on the surfaces of circuitlayers for the interchange of circuit layers with the same or differentfunctions from a preexisting inventory of circuit layers. The VSI finegrain vertical interconnections further are used for the functionalimplementation of arbitrarily wide high performance communicationprotocols, control and data information transfers, permanent ortemporary programming of control and data information between separatecircuit layers internal to a VSI IC. The VSI fine grain verticalinterconnections are further used as a means to establish physicalinterconnections for functional communication solely between any singlecircuit layer or a group of circuit layers and circuitry external to aVSI IC. The VSI fine grain vertical interconnections are further used asa means to establish through circuit design, in addition to theestablished means of fabrication process control, a reasonableexpectation of the percentage yield of a wafer of VSI IC circuitsindependent of the size in planar circuit area of the VSI IC.

Yield management circuitry is circuitry specific to the enhancement ofthe correct operation of a VSI IC or the yield of a wafer of VSI ICcircuits. The intention of this circuitry is to enable or disable,permanently or temporarily, one or more circuit elements or CircuitBlocks of a circuit layer or layers, or one or more whole circuit layersof a VSI IC circuit. This circuitry may or may not have circuit testcapability. This circuitry may be low in complexity such as a circuitfor switching signals from external circuitry for enabling or disablingvarious combinations of circuit elements, Circuit Blocks or circuitlayers via pass transistors, fuses or anti-fuses as examples.

In accordance with the VSI invention a yield enhancement can be achievedthrough circuit structure redundancy or sparing. The implementation ofredundant or spare circuitry increases the requirement for horizontalinterconnections on a planar circuit above existing interconnectionrequirements. This in and of itself makes most implementations of yieldimprovement through redundancy in planar circuits physicallyimpractical. However, there is also additional design complexity. TheVSI invention implements yield enhancement through redundant or sparecircuit structures placing these structures adjacent each other on thesame circuit layer or on separate circuit layers and enabling ordisabling them by control circuitry placed on a separate circuit layerand interconnected by fine grain vertical interconnections. Theplacement of the circuit spares and control circuitry on separatecircuit layers eliminates the need to use additional layers ofinterconnects and reduces design complexity by providing a standardizedinterconnection means. In this embodiment of the VSI invention, highdegrees of redundancy can be implemented without increased layers ofinterconnection or design complexity.

There is no more important circuit cost parameter than IC yield, even ifthe cost of fabricating circuit wafers were not significant, a near zeroyield still results in a high cost per unit IC before costconsiderations for IC packaging testing. IC yield is widely understoodto be the percentage of fully working finished circuits from a waferdivided by the total number of die available on the wafer. There areonly two ways to make a working IC, one is to fabricate without defect[perfect], and the second, is to “fix” the defective IC. The making ofperfect ICs is the preferred goal, rapidly evolving IC fabricationtechnology makes this an ever challenging goal. However, the smaller thedie size [and the more mature the fabrication process] the higher theprobability for perfect circuits [1 cm² seems to be one of those timeworn constants of the human universe, once you go beyond it, IC yielddrops at a near exponential rate]. This can be seen most clearly in themanufacture of planar DRAMs. High volume production of a DRAM does notbegin until the size of the die is less than 90-100 mm²; however, asignificant portion of planar DRAM circuits still require defect repairthrough sparing [redundant substitution] of the defective portion of theDRAM circuit.

If the more silicon used then the lower the circuit yield, whatadvantage is the VSI invention even if the physical circuit is spreadover several layers versus one large planar circuit? The answer is inthe novel circuit design architecture enabled by the VSI high densityvertical interconnect and small die size. PLD and memory circuits arevery regular in their organization and when stacked and organized abouta single control layer, naturally lend themselves to defect isolationand circuit reconfiguration to avoid defects. The VSI high densityvertical interconnect enables the communications between VSI circuitlayers without requiring additional horizontal interconnectmetallization layers per VSI circuit layer; fewer planar metallizationinterconnect layers enhance circuit yield and lower its fabricationcost. With this design method, one VSI circuit layer becomes theAchilles Heel for defects for the whole circuit, so the yield of a 400mm² circuit made from ten VSI circuit layers is determined by a single40 mm² “control” layer; taking this one step further, making the controllayer redundant will boost circuit yield.

The VSI invention for yield enhancement is through the novel applicationof its high density vertical bus interconnection, and smaller die sizewith increased circuit density due to shrinking fabrication geometries.Yields of large defect free planar ICs are low to zero with leading edgeprocesses. The yield of large planar ICs is achieved through the use ofredundant circuit blocks. This is typical of highly regular circuitslike DRAMs, Flash, and PLDs, where such circuits are physically repairedafter fabrication by replacing [reconfiguring] defective circuit blockswith redundant or spare circuit blocks by physically modifying thecircuit wiring. The VSI vertical bus is effectively “free”. This meansthat the amount of surface area required for a high density vertical busfor as many as 10,000 interconnections is very small and no additionalplanar interconnect layers are required; even when the vertical busesare fully redundant. This is important because logic chips like μPs arepresently approaching 9 and 10 layers of horizontal metal interconnectwhich leaves little room for horizontal reconfiguration interconnectionsand buses. Secondly, multiple copies of processing logic blocks[parallelism] are required to provide greater circuit performance, anddue to shrinking circuit geometries these logic blocks take less andless area. So, remembering silicon is cheap and one or more copies of acomplete logic function will fit on a VSI circuit layer, verticalreconfiguration buses enable a simple design method for VSI circuitrepair that is similar in its efficiency to what has been implemented inplanar memory ICs. The VSI repair method is dynamic and logical [notstatic and physical as in planar circuits] reconfiguration of failedcircuit logic blocks by reconfiguring or disabling the interconnectionsto failed circuit blocks through vertical bus connections. This meansthat 100% circuit redundancy is not necessary and that if a defectdevelops during the useful life of a circuit, it may be able toreconfigure [repair] itself or achieve a degree of fault tolerantcapability.

The VSI invention provides the capability for wafer to wafer alignmentthat scales with the reducing geometry of the horizontalinterconnections of planar semiconductor fabrication processes.Presently available wafer to wafer alignment technology intended for thepre-bonding of wafers supports the use of fine grain verticalinterconnection minimum pitch of 2-3 μm which is 8 to 12 times greaterthan the minimum horizontal interconnect pitch of present state of theart semiconductor processes which have a minimum feature size 150 nm[0.15 μm]. FIG. 8 shows horizontal 81 a, 81 b and 81 c and vertical 82a, 82 b and 83 interconnections with equal spacing pitch. In order forfine grain vertical interconnect to most efficiently integrate withhorizontal interconnection processes the vertical interconnection pitchshould be approximately equal to or less than the pitch of the lasthorizontal metal interconnection layer as shown in FIG. 8; the lasthorizontal interconnection layer may or may not be the VSI bond layer. Asimilar or compatible scaling of fine grain vertical interconnectionsenables the efficiency and capacity of VSI IC integration. The finegrain vertical pitch capability of the of the VSI invention can scalewith anticipated geometry reductions of horizontal interconnections to aminimum feature size of less than 100 nm and less than 50 nm due to theenabling capability of the VSI wafer and substrate alignment methoddescribed herein. The VSI IC fine grain vertical interconnections havethe novel and unique advantage of being able to support higher currentflows that may be required when stacking such circuitry as multiple highoperating frequency microprocessors or analog circuitry. This advantageresults from the ability of VSI IC fine grain vertical interconnections83 to be formed with arbitrarily high cross section aspect ratios in arange such as from 4:1 and exceeding 80:1, and thereby creating avertical wire between circuit layers with a cross-sectional area largeenough to carry more than 100 times the current of horizontal signalwires or approximately the current carried by present 25 μm diameterpackaging bond wires. The methods used for making fine grain verticalinterconnections with high cross section aspect ratios are the same asthose used for making vias on planar ICs.

The VSI invention's capability to achieve wafer to wafer alignment finegrain vertical interconnection contacts of less than 50 to 100 nm pitch,enables a reduction in the number horizontal interconnection layerstypically required for global or cross die interconnections. The VSI ICintegration density is further increased when fabricated with SOI wafersor wafers with a buried etch stop layer or wafers or substrates madefrom two or more distinct materials such as Silicon on glass or GaAs onSilicon. This increase in integration results from thinner remainingsemiconductor substrate enabling smaller vertical interconnection pitchthrough the remaining substrate.

The VSI IC integration uniquely enables or enhances the fabrication of awide range of electronic and MEMS products. The principle results ofapplying the VSI IC circuit development and manufacturing methods are:

-   -   1. Reduced product design or architecture complexity,    -   2. Reduced product development complexity,    -   3. Increased technology, process and IP integration,    -   4. Reduced manufacturing tooling,    -   5. Reduced net circuit power dissipation,    -   6. Higher circuit yields, and    -   7. Higher overall circuit performance.

VSI IC integration enables the structuring of various circuit functiontypes as one or more circuit layers that can subsequently andarbitrarily be integrated into a final VSI component product. Thesecircuit function types are presently implemented as separate planarcircuits. The VSI IC capability to Closely Couple any and all of thenumerous wide ranging circuit function types and MEMS devices results inthe same operational benefits of an as if planar circuit and or MEMSintegration. A partial listing of circuit function or MEMS device typesthat can be integrated into a VSI IC consists of CAMs [ContentAddressable Memories], network specific processing functions, DRAMs,flash, non-volatile memories, DSPs, microprocessors, PLDs, CPLDs, FPGAs,Serdes [serializer deserializer], CCD or CMOS video imaging sensorarrays, and MEMS devices such as DMDs [Digital Micromirror Devices],antennas, micro-gryos, inkjet nozzle arrays, free air inductors, microswitches, IC probes, accelerometers or microphones.

Additional aspects of the invention include:

-   -   1. An integrated circuit layer optimized for vertical system        integration, comprising at least one vertical bus standardized        with respect to at least one other completed physical IC design        or fabricated IC.    -   2. A full-chip integrated circuit design optimized for vertical        system integration, comprising at least one vertical bus        standardized with respect to at least one other completed        physical IC design or fabricated IC.    -   3. A stacked integrated circuit having at least partial logic        circuit redundancy between different layers.    -   4. A stacked integrated circuit comprising at least three        layers, each of the three layers being either a memory layer or        a PLD or FPGA circuit layer.    -   5. The apparatus of claim 4, comprising a plurality of memory        layers and a plurality of PLD or FPGA circuit layers.    -   6. A method of information processing using an array of        processor modules, comprising:        -   providing each wireless processor with wireless            interconnection capability; and        -   each processor module using wireless interconnection for the            transmission of information or data.    -   7. The method of claim 6, wherein at least one of the processor        modules comprises a stacked integrated circuit.    -   8. The method of claim 7, wherein at least one wireless        interconnection path is an adaptive antenna path.    -   9. The method of claim 7, wherein the processor modules are less        than three cubic inches in volume.    -   10. The method of claim 7, wherein wireless transmission paths        are formed between processor modules on demand.    -   11. The method of claim 7, wherein a processor modules has        multiple concurrent wireless interconnections.    -   12. The method of claim 7, wherein at least some of the        interconnection paths are programmably reconfigured through        cooperation of two or more processor modules.    -   13. The method of claim 7, comprising providing means for        establishing interconnections paths between each of a plurality        of processor modules and every other processing modules in the        array.    -   14. A computational system comprising an array of processor        modules which use wireless interconnections for the transmission        of information or data.    -   15. Internet Protocol switching equipment comprising an array of        processors wherein routing of IP messages between processors is        performed with wireless transmission.    -   16. A computational system comprising an array of parallel        processors interconnected with wireless interconnections.    -   17. A computational system comprising multiple processors and        means for establishing a point-to-point transmission path        between any two processors.    -   18. A computational system comprising multiple processors and        means for establishing interconnection paths between the        processors, further comprising means for programmably        reconfiguring a plurality of the interconnection paths on        demand.    -   19. A method of making a stacked ASIC comprising:        -   for at least one layer of the stacked ASIC, using a            completed physical IC design or fabricated IC designed prior            to design of the stacked ASIC.    -   20. The method of claim 19, wherein the the completed physical        IC design or fabricated IC is selected from a standard library        of circuit layers.    -   21. The method of claim 20, wherein the standard library of        circuit layers includes PLD or FPGA circuitry.    -   22. The method of claim 21, wherein the completed physical IC        design or fabricated IC includes PLD or FPGA circuitry.    -   23. The method of claim 19, comprising:        -   for at least one other layer of the stacked ASIC, designing            a custom design at the time of design of the stacked ASIC.    -   24. A method of using a stacked ASIC having at least one layer        of PLD or FPGA circuitry and at least one layer of memory,        comprising programming a PLD or FPGA layer from a memory layer.    -   25. The method of claim 24, the stacked ASIC has at least one        layer having fixed logic functions.    -   26. The method of claim 25, wherein the layer having fixed logic        functions is a microprocessor.    -   27. A method of reducing signal path skew from a planar circuit,        comprising stacking portions of the planar circuit to form a        stacked IC, thereby shortening the skewed signal path length.    -   28. A stacked IC forming its own package, comprising a plurality        of circuit layers bonded together such that no circuitry of a        circuit layer of the IC is external to the IC.    -   29. A method of making a stacked IC, comprising bonding together        a plurality of circuit layers such that no circuitry of a        circuit layer of the IC is external to the IC, whereby the        stacked IC forms its own package.    -   30. A method of making a stacked IC, comprising:        -   forming a first circuit layer;        -   thinning the first circuit layer;        -   performing back-side processing of the first circuit layer            to relocate at least one a vertical interconnect from a            first previously-determined location to a second different            location; and        -   bonding the first circuit layer to a second circuit layer.    -   31. A method of using a stacked IC having a plurality of circuit        layers, comprising using control circuitry on one or more of the        circuit layers to enable or disable the use of at least a        portion of another circuit layer.    -   32. A method of controlling the power dissipation of a stacked        IC having a plurality of circuit layers comprising, during        operation of the stacked IC, removing power to one or more of        the circuit layers such that they have insufficient power to        operate.    -   33. A method of fabricating a stacked IC having a plurality of        circuit layers, comprising:        -   bonding the circuit layers using an inorganic thermal            diffusion bonding process;        -   thinning at least one circuit layer from the backside            thereof; and        -   on the backside of the at least one circuit layer,            fabricating at least one of active circuit devices, passive            circuit devices and horizontal interconnections.    -   34. A method of fabricating a stacked IC comprising:        -   stacking a plurality of ICs to form a stacked IC having            substantially the same functionality as a plurality of            planar ICs, the planar ICs having a total of N external I/O            connects;        -   wherein the stacked IC has substantially fewer than N            external I/O connects.    -   35. A method of information processing using a stacked IC having        a plurality of circuit device layers, wherein operation of at        least one circuit device layer requires that at least one other        circuit layer be present.    -   36. The method of claim 35, wherein at least one of the circuit        device layers comprises electronic circuitry.    -   37. The method of claim 35, wherein at least one of the circuit        device layers comprises optical circuitry.    -   38. The method of claim 35, wherein at least one of the circuit        device layers comprises a MEMS device.    -   39. An integrated circuit comprising:        -   a supporting substrate;        -   at least one thinned IC bonded face down on the supporting            substrate; and        -   at least one external I/O contact formed on the backside of            the thinned IC.    -   40. The apparatus of claim 39, wherein the supporting substrate        is a heat sink.    -   41. A method of making a circuit layer of a stacked IC, wherein        the circuit layer is fabricated using a substrate having a        plurality of barrier layers formed therein.    -   42. An integrated circuit die having a plurality of circuit        layers with circuitry thereon, wherein the surface area of the        circuit of the circuit layers is substantially greater than the        surface area of the integrated circuit die.    -   43. A stacked IC having a plurality of circuit layers wherein IC        device fabrication is performed on the backside of one or more        circuit layers.    -   44. The apparatus of claim 43, wherein the IC devices comprise        at least one of the following: transistors, memory cells,        resistors, capacitors, inductors, radio frequency antennas and        horizontal interconnections.    -   45. The apparatus of claim 43, wherein the IC devices comprise        at least two of the following: transistors, memory cells,        resistors, capacitors, inductors, radio frequency antennas and        horizontal interconnections.    -   46. The apparatus of claim 43, wherein the IC devices comprise        all of the following: transistors, memory cells, resistors,        capacitors, inductors, radio frequency antennas and horizontal        interconnections.    -   47. A stacked IC having a plurality of circuit layers including        at least two of the following: electronic, optical and MEMS        circuit layers.    -   48. Method of making a stacked IC having a plurality of circuit        layers without fabrication of a circuit layer specific to the        function of the particular stacked IC.    -   49. Method of making a stacked IC having a plurality of circuit        layers where fewer than all of the circuit layers are fabricated        for the specific function of the particular stacked IC.    -   50. A IC device wherein the die size is less than the area of        the total circuitry of the integrated circuit device.    -   51. A stacked IC having a plurality of circuit layers wherein        horizontal IC interconnection fabrication is performed on the        backside of one or more the circuit layers.    -   52. A stacked IC having a plurality of circuit layers wherein        one or more the circuit layers is thinned by removing the        substrate to a barrier layer comprising a thin dielectric layer.    -   53. The apparatus of claim 52, wherein the thin dielectric layer        thickness is less than 100 Å.    -   54. The apparatus of claim 52, wherein the thin dielectric layer        thickness is less than 200 Å.    -   55. The apparatus of claim 52, wherein the thin dielectric layer        thickness is in a range of 50 Å to 500 Å.    -   56. A stacked IC having a plurality of circuit layers wherein a        dielectric layer is deposited on the backside of one or more the        circuit layers to enhance electrical isolation of an underlying        semiconductor device layer.    -   57. A stacked IC having a plurality of circuit layers wherein IC        device fabrication is performed on the backside of one or more        circuit layers to complete the fabrication of IC devices        partially formed on the front side of the one or more circuit        layers.    -   58. A stacked IC having a plurality of circuit layers wherein IC        fabrication is performed on the backside of one or more the        circuit layers to fabricate one or more layer memory layers.    -   59. The apparatus of claim 58, wherein the memory layers consist        of at least one of MRAM, PRAM, ferroelectric or dendritic        memory.    -   60. A stacked IC having a plurality of circuit layers wherein        the use of vertical interconnections replace one or more of the        following: IC packages, IC sockets, PCBs and PCB edge        connectors.    -   61. A stacked IC having a plurality of circuit layers wherein        the circuit layers are bonded using bonding layers made from two        or more metal films one of which has a lower melting point and        which will diffuse with an immediately adjacent film.    -   62. The apparatus of claim 61, wherein bonding layers form a        diffused metal film having a higher melting point than the lower        melting point metal film.    -   63. A method of bonding IC substrates using at least two metal        films with different melting points on each surface of the        substrates to be bonded wherein during or after bonding of the        substrates the metal films diffuse to form one metal film with a        melting point that is higher than the lower melting point of the        original two metal films.    -   64. A stacked IC having a plurality of circuit layers bonded        using one or more bonding layers made from Sn and Al films        wherein the Sn film prevents the formation of Al oxide on the Al        film and diffuses into the Al film when bonded to another        circuit layer.    -   65. A method of making a stacked IC having a plurality of        circuit layers comprising:        -   making design changes to a circuit layer;        -   causing the circuit layer to be fabricated; and        -   stacking the circuit layer together with a plurality of            other previously-fabricated circuit layers;        -   wherein the design changes to the circuit layer do not            require the other circuit layers be fabricated again.    -   66. A stacked IC having a plurality of PLD or FPGA circuit        layers wherein there is a greater amount of stacked PLD or FPGA        circuitry than can be fabricated as one planar PLD or FPGA        circuit.    -   67. A stacked IC having a plurality of circuit layers wherein        there is a greater amount of stacked circuitry than can be        fabricated as one planar circuit.    -   68. A stacked IC having a plurality of circuit layers wherein        one or more groups of vertical interconnections have standard        placement for coupling with such groups of vertical        interconnections formed on adjacent circuit layers.    -   69. A method of making an IC wherein the die size of the IC is        not determined by an amount of circuitry comprising the IC.    -   70. A method of making a stacked IC that has reduced die size        and hence reduced power dissipation as compared to an        equivalent-function planar IC.    -   71. A stacked IC having a plurality of circuit layers wherein at        least one of the circuit layers is a programmable tester for        testing of the stacked IC during burn-in or during its useful        life.    -   72. A stacked IC having a plurality of circuit layers wherein        all surfaces of the circuit layers with circuitry thereon are        internal to the stacked IC whereby the stacked IC is its own        packaging.    -   73. The apparatus of claim 72, wherein the bonding layers of all        of the circuit layers form hermetic seals.    -   74. A method of making a stacked IC having a plurality of        circuit layers wherein vertical interconnection of circuitry is        used to reduce the number of horizontal interconnection layers        on one or more of the circuit layers.    -   75. A method of increasing the I/O bandwidth between separate        ICs by stacking the ICs to allow the number of interconnections        between the ICs and the transfer rate of each interconnection to        be increased without an increase in dedicated I/O circuitry.    -   76. A stacked IC having a plurality of circuit layers wherein        two or more circuit layers have similar functioning circuitry in        a vertical overlapping position.    -   77. A stacked IC having a plurality of circuit layers wherein        the yield of the stacked IC is primarily determined by the yield        of specific circuit layers designed specifically for a plurality        of circuit layers of the particular stacked IC, and wherein the        specific circuit layers are half or less of the number circuit        layers of the stacked IC.    -   78. A stacked IC having a plurality of circuit layers wherein        the circuitry on the circuit layers is reconfigurable by the use        of vertical interconnections between the circuit layers.    -   79. A stacked IC having a plurality of circuit layers wherein        one or more vertical interconnections between the circuit layers        have cross-sectional areas that are at least two times larger        than any horizontal signal interconnection.    -   80. A stacked IC having a plurality of circuit layers wherein        some of the circuit layers are not designed specifically for the        particular stacked IC.    -   81. A stacked IC having a plurality of circuit layers wherein an        application-specific function of the stacked IC is derived from        the choice and quantity of circuit layers from        previously-fabricated, non-application-specific circuit layers.    -   82. A stacked IC having a plurality of circuit layers wherein        one or more of the circuit layers have portions of horizontal        interconnections that are free-standing.    -   83. A stacked IC having a plurality of circuit layers wherein        one or more of the circuit layers have portions of horizontal        interconnections that are without the mechanical support of a        dielectric.    -   84. A method of fabricating a circuit assembly comprising        aligning and bonding a plurality of dice face down to the        substrate, depositing one or more layers of dielectric material        over the substrate and dice, and thinning a majority of the        substrate of the dice so that a finished thickness of the dice        and dielectric material between the dice are approximately        equal.    -   85. The method of claim 84, wherein the thickness of the        dielectric material deposited is approximately the final        thickness that the dice are to be thinned to.    -   86. A stacked IC having a plurality of circuit layers wherein        one or more of the circuit layers can be reused in at least one        other stacked IC without requiring the redesign of the one or        more circuit layers.    -   87. A stacked IC having a plurality of circuit layers wherein        interconnections of circuitry on at least one of the circuit        layers are changed by interconnections on the backside of the        circuit layer.    -   88. A method of making a stacked IC having a plurality of        circuit layers wherein the stacked IC is made through the use of        a stacked IC platform including reusable circuit layer designs.    -   89. A method of processing both sides of an IC substrate having        a frontside and a backside wherein the IC substrate is bonded        face down onto a second substrate and the backside of the IC        substrate is thinned to a thickness that permits conventional IC        fabrication processing, comprising forming interconnections        between circuitry on the frontside of the IC substrate with the        circuitry formed on the backside of the IC substrate.    -   90. A stacked IC having a plurality of circuit layers wherein        the yield of the stacked IC is determined by the yield of each        of the plurality of circuit layers.    -   91. The apparatus of claim 90, wherein the plurality of circuit        layers each have different yields.    -   92. A stacked IC having a plurality of circuit layers wherein        the yield of one or more of the circuit layers is determined at        least in part by the yield of one or more fully redundant        circuit layers of the plurality of circuit layers of the stacked        IC.    -   93. The apparatus of claim 92, wherein the yield of the fully        redundant circuit layer is determined by the yield of two or        more sub-portions of the fully redundant circuit layer.    -   94. A stacked IC having a plurality of circuit layers wherein        one or more transistor gates of at least one circuit layer is        back biased by forming a contact on the backside of the at least        one circuit layer opposite the one or more transistor gates.    -   95. A stacked IC having a plurality of circuit layers wherein        the yield of the stacked IC is increased by the addition of one        or more redundant circuit layers of one of the plurality of        circuit layers of the stacked IC and wherein the redundant        circuit layers are immediately adjacent and overlapping.    -   96. A stacked IC having a plurality of circuit layers wherein        I/O drivers for the stacked IC are physically on a separate        circuit layer or on the backside of one of the circuit layers.    -   97. A stacked IC having a plurality of circuit layers wherein in        one of the circuit layers the dielectric has been predominately        removed leaving free-standing metal horizontal and vertical        interconnections.    -   98. A stacked IC having a plurality of circuit layers wherein        one of the circuit layers contains a predominately free-standing        Rf antenna.    -   99. A stacked IC having a plurality of circuit layers wherein        one of the circuit layers comprises a MEMS device.    -   100. The apparatus of claim 99, wherein the first circuit layer        is a MEMS device.    -   101. The apparatus of claim 99, wherein the MEMS device is        fabricated as part of a circuit layer after bonding of the        circuit layer to another circuit layer.    -   102. A stacked IC having a plurality of circuit layers wherein        one optical circuit layer couples signals into an electronic        circuit layer.    -   103. A stacked IC having a plurality of circuit layers wherein        one electronic circuit layer couples signals into an optical        circuit layer.    -   104. A stacked IC having a plurality of circuit layers wherein        one of the circuit layer is a generically programmable automatic        testing circuit layer for testing one or more of the circuit        layers of the stacked IC.    -   105. A method of enhancing the yield of a stacked IC having a        plurality comprising simultaneously increasing the number of        circuit layers and reducing the die size of the circuit layers.    -   106. A method of enhancing the yield of a stacked IC diced from        a stacked IC substrate having a plurality of circuit layers        comprising simultaneously reducing the die size of the circuit        layers and increasing the number of stacked ICs diced from the        stacked IC substrate.    -   107. A method of enhancing the yield of a stacked IC having a        plurality of circuit layers comprising using one circuit layer        with less processing complexity than the other circuit layers.    -   108. A method of enhancing the yield of a stacked IC having a        plurality of circuit layers comprising separating at least one        circuit layer into two or more circuit layers with less        processing complexity.    -   109. A stacked IC having a plurality of circuit layers wherein        operation of the stacked IC is unchanged when one or more        circuit layers incorporate and use redundant circuitry.    -   110. A stacked IC having a plurality of circuit layers with        redundant circuits wherein an interconnection wire length        between redundant circuits is approximately equal to or less        than a thickness of the stacked IC.    -   111. A stacked IC having a plurality of circuit layers including        wireless circuitry for creating multiple data transmission paths        between a plurality of stacked ICs, comprising means for        changing a number of wireless data transmission paths between        any two stacked ICs as needed.    -   112. A stacked IC having a plurality of circuit layers including        a plurality of wireless circuits wherein the wireless circuits        are used to create a plurality of data transmission paths.    -   113. An array of processing modules each including wireless        circuitry wherein the wireless circuitry can create at least one        point-to-point data transmission path between each of a majority        of the processing modules of the array.    -   114. Internet Protocol router equipment comprising a plurality        of processing modules having a plurality of wireless        communication circuits wherein the router data processing is        primarily performed by the processing modules having wireless        communication circuits.    -   115. Data processing equipment comprising a plurality of        processing modules having a plurality wireless communication        circuits wherein the data processing is primarily performed by        the processing modules having wireless communication circuits.    -   116. Data processing equipment comprising a plurality of        processing modules having a plurality of wireless communication        circuits wherein the wireless communication circuits of the        processing modules are used for at least one of: 1) recovering        from a failure of the wireless communication circuits in one of        processing modules and 2) recovering from a failure of one of        the wireless communication circuits in one of the processing        modules to provide a required rate of data transmission.    -   117. A stacked IC having a plurality of circuit layers wherein        an area of the circuit layers is greater than a planar circuit        having an area of 800 mm2.    -   118. A PD MOS transistor having a bias electrode formed opposite        the transistor channel of a fabricated transistor, on an        underside of the fabricated transistor.    -   119. A dual gate transistor wherein the gates are adjacent        V-groove structures formed from opposite sides of the transistor        body.    -   120. A method of reducing the substrate leakage of a MOS        transistor comprising providing a dielectric block under a gate        of the MOS transistor.    -   121. A method of reducing the substrate leakage of a MOS        transistor comprising providing a V-groove shaped dielectric        block under a gate of the MOS transistor.    -   122. A method of reducing the substrate leakage of a MOS        transistor comprising providing a V-groove gate under a gate of        the MOS transistor.    -   123. A method of reducing the substrate leakage of a MOS        transistor comprising providing a block shaped gate under a gate        of the MOS transistor.    -   124. A memory cell comprising one transistor and one capacitor        wherein the capacitor is fabricated on a backside of the        transistor after the transistor is fabricated and after a        majority of the substrate of the transistor has been removed.    -   125. A memory cell comprising at least one transistor and a        contact coupled to the transistor from a backside of the        transistor.    -   126. A MOS transistor comprising a floating gate under a gate of        the transistor, the floating gate being formed from the backside        of the transistor.    -   127. A non-volatile EEPROM memory cell comprising two floating        gates positioned vertically with respect to each other.    -   128. A non-volatile EEPROM memory cell comprising two opposed        gates positioned vertically wherein the one of the gates enables        a charge level of the EEPROM memory cell to be changed during        use of the EEPROM memory cell.    -   129. A quad gate transistor comprising a vertical transistor        body.    -   130. A memory cell comprising a single vertical transistor and a        quad gate.    -   131. A stacked IC comprising a plurality of circuit layers        having redundant circuitry wherein the stacked IC will function        if two or more circuit layers having redundant circuitry are        used.    -   132. A method of making a stacked IC having a plurality of        circuit layers, wherein the circuit layers are provided from an        inventory of substrates with completed circuitry thereon.    -   133. A method of performing image positioning and        demagnification of a lithographic on a substrate wherein the        image is adjusted based on temperature of the substrate.    -   134. A method of aligning two substrates or wafers having        circuitry thereon for bonding, wherein an opening is made from a        backside of one of the substrates or wafers to be bonded to        expose an alignment mark, thereby allowing the use of optical        alignment methods.    -   135. A method of aligning two substrates or wafers with        circuitry thereon for bonding, wherein an opening is made from a        backside forming an opening on the front side of one of the        substrates or wafers to be bonded exposing an alignment mark,        and using an atomic force microscope to access alignment marks        on both substrates or wafers at the same time.    -   136. An apparatus for full wafer test and burn-in wherein        circuitry for performing full wafer test and burn-in comprises a        stack of thinned circuit wafers.    -   137. A stacked IC having a plurality of circuit layers including        memory control logic and memory circuit layers wherein at least        one circuit layer has memory control logic circuitry enabling        reconfiguration of the memory circuit layers of the stacked IC.    -   138. A stacked IC having a plurality of circuit layers including        memory control logic and memory circuit layers wherein at least        one circuit layer has memory control logic circuitry enabling        the use of a variable amount of the memory of the stacked IC.    -   139. A credit-card-shaped enclosure comprising one or more        stacked ICs having a processing capacity equivalent to a typical        desktop computer.    -   140. A credit-card-shaped enclosure comprising one or more        stacked ICs having general purpose processing capacity for use        with a plurality of peripheral equipment.    -   141. A method of controlling a plurality of peripheral equipment        using the same computer control and storage electronics        assembled in a card package which are inserted into the        peripheral equipment for controlling same when needed.    -   142. A method of packaging software wherein the software is        enclosed in a portable electronic card capable of executing the        software at a desired speed.    -   143. A sensing device with sensor devices separated and        overlying processing electronics of the sensor devices.    -   144. A stacked programmable logic device having a plurality of        circuit layers wherein there is at least one each of a        programmable gate circuit layer, a routing circuit layer and a        memory circuit layer.    -   145. A stacked programmable logic device having a plurality of        circuit layers wherein there is at least one circuit layer        comprising automatic test electronics.    -   146. A method of increasing programmable logic capacity of a        stacked programmable logic device having at least one of a        programmable gate circuit layer and a memory circuit layer,        comprising adding to the stacked programmable logic device one        or more programmable gate circuit layers or memory circuit        layers.    -   147. A stacked IC having a plurality of circuit layers with        processors thereon wherein a non-blocking cross bar        interconnects the processors and is integrated onto the circuit        layers of the stacked IC.    -   148. A stacked IC having a plurality of circuit layers wherein        one or more of the circuit layers comprises analog circuitry        elements and one or more of the circuit layers comprises        reconfigurable circuitry which can be programmed to interconnect        the analog circuitry elements to circuitry on one or more of the        circuit layers of the stacked IC.    -   149. A stacked IC having a plurality of circuit layers wherein        one or more of the circuit layers comprises passive circuitry        elements and one or more of the circuit layers comprises        reconfigurable circuitry which can be programmed to interconnect        the passive circuitry elements to circuitry on one or more of        the circuit layers of the stacked IC.

BRIEF DESCRIPTION OF DRAWINGS

The present invention may be further understood from the followingdescription in conjunction with the appended drawings. In the drawing:

FIG. 1 is a cross section of horizontal interconnections of a planar IC.

FIG. 2A is a cross section of a two layer VSI IC.

FIG. 2B is a cross section of a three layer VSI IC.

FIG. 2C is top view of predefined or standardized placement of verticalinterconnection blocks on a VSI circuit layer.

FIG. 3 is a pictorial view of a VSI Application Specific IC withComponent MEMS device, CMOS, bipolar and optical circuit layers.

FIG. 4 is a pictorial view of a VSI Non-application Specific IC orComponent and Function Layer Groups.

FIG. 5 is a pictorial view of a VSI IC or Component and ApplicationSpecific and Non-application Specific Function Layer Groups.

FIG. 6 is a cross section of a VSI IC with test and yield enhancementcircuit layers.

FIG. 7A is a cross section of a VSI IC with MEMS and low-K dielectriccavities.

FIG. 7B is a cross section of a VSI IC with VSI die bonded onto a VSIIC.

FIG. 7C is a top view of individual vertical interconnection contactspatterned into a bonding layer.

FIG. 7D is a cross section of a VSI wafer stack during fabrication of abonded die assembly circuit layer.

FIG. 7E is a cross section of a VSI wafer stack during fabrication of abonded die assembly circuit layer.

FIG. 7F is a cross section of a VSI wafer stack of a completed bondeddie assembly circuit layer as the first VSI circuit layer.

FIG. 8 is a layout view of horizontal and vertical interconnections withequal pitch spacing.

FIG. 9 is a cross section of a VSI double layer SOI substrate.

FIG. 10 is a cross section of a VSI IC mounted on a support substratewith optical fiber interconnections.

FIG. 11A is a cross section of a VSI IC with use of fine grain verticalinterconnection redundancy.

FIG. 11B is a cross section of placement of redundant circuitry on aplanar IC.

FIG. 11C is a cross section of placement of redundant circuitry in a VSIIC.

FIG. 11D is a pictorial view of a VSI Wireless InterconnectMultiprocessor Computing System.

FIG. 11E is a pictorial view of a VSI Wireless Interconnectmultiprocessor Computing System.

FIG. 11F is a pictorial view of a VSI Wireless Interconnect IP Routerand Switching System.

FIG. 11G is a pictorial view of a VSI Wireless Interconnect ThreeDimensional Super Computer System.

FIG. 12 is a cross section of a dual gate V-groove MOS transistor.

FIG. 13 is a cross section of a dual gate V-groove MOS transistor.

FIG. 14 is a cross section of prior art SOI MOS transistor in a VSIcircuit layer.

FIG. 15A is a cross section of prior art MOS transistor showingsubstrate leakage path.

FIG. 15B is a cross section of prior art SOI MOS transistor.

FIG. 15C is a cross section of a VSI SOI transistor with SLB.

FIG. 15D is a cross section of a VSI SOI transistor leakage path trench.

FIG. 15E is a cross section of a partially formed VSI double gate MOStransistor.

FIG. 15F is a cross section of a VSI double gate sub-optical MOStransistor.

FIG. 15G is a cross section of a VSI double contact source drain MOStransistor.

FIG. 16A is a cross section of a prior art PD SOI MOS transistor.

FIG. 16B is a cross section of a prior art PD SOI MOS transistor withVSI substrate leakage barrier.

FIG. 16C is a cross section of a VSI double gate PD MOS transistor withSLB.

FIG. 17A is a cross section of a partially completed VSI MOS transistor.

FIG. 17B is a cross section of a VSI MOS transistor.

FIG. 18A is a cross section of a VSI 1T1C low substrate leakage cell.

FIG. 18B is a cross section of a VSI 1T DRAM cell.

FIG. 19A is a cross section of a dual function transistor EEPROM device.

FIG. 19B is a cross section of a dual function transistor EEPROM device.

FIG. 19C is a cross section of a dual gate EEPROM device.

FIG. 19D is a cross section of a dual gate EEPROM device.

FIG. 19E is a top view of a VSI dual function circuit device.

FIG. 19E-AA is a cross section of a VSI dual function circuit device.

FIG. 19E-BB is a cross section of a VSI dual function circuit device.

FIG. 19F1 is a cross section of a Quad-Gate transistor fabrication step.

FIG. 19F2 is a cross section of a Quad-Gate transistor fabrication step.

FIG. 19F3 is a cross section of a Quad-Gate transistor fabrication step.

FIG. 19F4 is a cross section of a Quad-Gate transistor fabrication step.

FIG. 19F5 is a cross section of a Quad-Gate transistor.

FIG. 19G1 is a cross section of a Quad-Gate transistor fabrication step.

FIG. 19G2 is a cross section of a Quad-Gate transistor fabrication step.

FIG. 19G3 is a cross section of a Quad-Gate transistor fabrication step.

FIG. 19G4 is a cross section of a Quad-Gate transistor fabrication step.

FIG. 19G5 is a cross section of a Quad-Gate transistor.

FIG. 19H is a cross section of a Quad-Gate 1T Memory Cell.

FIG. 20A through 20F are cross sections of a VSI EEPROM emitterfabrication sequence.

FIG. 21A is a cross section of a VSI optical substrate alignment method.

FIG. 21B is a cross section of a VSI optical substrate alignment method.

FIG. 21C is a cross section of a VSI optical substrate alignment method.

FIG. 21D is a cross section of a VSI optical split field substratealignment method.

FIG. 22A is a top view of overlapping alignment marks.

FIG. 22B is a cross section of a VSI substrate alignment method with aAFM probe.

FIG. 23A is a cross section of VSI ATE system circuitry.

FIG. 23B is a cross section of VSI ATE system circuitry mounted on asupport substrate.

FIG. 23C is a cross section of VSI ATE system circuitry mounted on asupport substrate.

FIG. 24A is a planar circuit layout of a reconfigurable memory.

FIG. 24B is a sequence of reconfigurable memory layers.

FIG. 24C is reconfigurable memory circuit layer layout of memory arrayblocks.

FIG. 24D is a layout showing VSI configurable memory gate line routerand sparing.

FIG. 24E is a layout showing VSI configurable memory data line routerand sparing.

FIG. 25A is cross section of a VSI photo sensing circuit.

FIG. 25B is cross section of a VSI photo sensing circuit for multiplewavelengths.

FIG. 26A is a cross section of a VSI FPGA IC.

FIG. 26B is a cross section of a VSI FPGA IC.

FIG. 27 is the diagram of the circuit layer stacking order of a VSIInternet Protocol communication processing IC.

FIG. 28 is a cross section of a VSI optical waver guide interconnection.

FIG. 29 is a cross section of a VSI optical waver guide couplinginterconnection.

ADDITIONAL ASPECTS AND OBJECTIVES OF THE VSI INVENTION

It is an aspect and objective of the VSI invention to provide a meansfor the fabrication of application specific ICs [ASICs] or customintegrated circuits and or Application Specific Standard Product [ASSP]ICs without the present requirement for customized circuit design andlayout or fabrication tooling.

It is a further aspect and objective of the VSI invention to provide ameans for the integration of electronic, optical and MEMS device typesas closely coupled separate device layers as a single data processingsystem or sub-system component.

It is a further aspect and objective of the VSI invention to provide amethod for achieving high yields of VSI components.

It is a further aspect and objective of the VSI invention to provide ameans to make electronic or optical components customized for specificapplications from previously fabricated device layers.

It is a further aspect and objective of the VSI invention to provide oneor more circuit test and configuration control layers connected by finegrain vertical interconnections to improve circuit yield, powerdissipation and operational function.

It is a further aspect and objective of the VSI invention to provide ameans for design of circuit development platforms for the rapiddevelopment of application specific products.

It is a further aspect and objective of the VSI invention to provide ameans for the reduction of integrated circuit architectural, design anddevelopment complexity. It is a further aspect and objective of the VSIinvention to provide a means for the incorporation and reuse of hardwarefunction IP [Intellectual Property] without requiring circuit designchanges, synthesis and timing analysis.

It is a further aspect and objective of the VSI invention to provide ameans for the alignment of wafer or substrates prior to bonding to anaccuracy of less than ±1 μm and less than ±500 nm and less than ±100 nm.

It is a further aspect and objective of the VSI invention to provide amethod of VSI device layer fabrication with the use of multiple barrierlayers.

It is a further aspect and objective of the VSI invention to provide amethod of IC fabrication from a physical circuit library.

It is a further aspect and objective of the VSI invention to provide amethod of IC self packaging.

It is a further aspect and objective of the VSI invention to provide ameans for generic IC internal testing.

It is a further aspect and objective of the VSI invention to provide ameans to eliminate design restrictions on interconnect memory accessbandwidth.

It is a further aspect and objective of the VSI invention to provide ameans for proscribed maximum interconnect lengths.

It is a further aspect and objective of the VSI invention to provide ameans for fabricating ICs with a die size independent of total circuitsurface area.

It is a further aspect and objective of the VSI invention to provide ameans for IC design with a predictable net circuit yield.

It is a further aspect and objective of the VSI invention to provide ameans for integration of incompatible circuit fabrication technologiesand processes.

It is a further aspect and objective of the VSI invention to provide ameans for reduction or elimination of mask tooling requirements per ICfabrication sequence.

It is a further aspect and objective of the VSI invention to provide ameans for reduction of circuit fabrication complexity of large ICs.

It is a further aspect and objective of the VSI invention to provide ameans of reduction or elimination of the leakage path between the sourceand drain of a MOS transistor.

It is a further aspect and objective of the VSI invention to provide amethod for making a gate on the backside of the transistor body.

It is a further aspect and objective of the VSI invention to provide amethod for making an EEPROM memory cell.

It is a further aspect and objective of the VSI invention to provide amethod for making an EEPROM memory cell that is written and erased fromthe PG and is not programmed through the gate dielectric of the device.

It is a further aspect and objective of the VSI invention to provide amethod for making an EEPROM memory cell that can be set to a precisecharge value or by a write or erase operation eliminating the need for afull erase operation.

It is a further aspect and objective of the VSI invention to provide amethod for making an EEPROM memory cell with a dual programmable gatestructure.

It is a further aspect and objective of the VSI invention that theprocessor modules of an array of processor modules can form wirelesspoint-to-point interconnection paths between any and all of theprocessor modules.

It is a further aspect and objective of the VSI invention to provide apoint-to-point wireless communication means between the processormodules of an array of processor modules to enable the processor tooperate at approximately their designed performance capacity.

It is a further aspect and objective of the VSI invention to provide apoint-to-point wireless communication means between the processormodules of an array of processor modules that reduces the distance, andtherefore, the time to transmit information signals or data between anytwo of the processor modules.

It is a further aspect and objective of the VSI invention to provide ameans for changing the position of processor modules of an array ofprocessor modules without interruption of the operation of the array ofprocessor modules providing a high availability or non-stop processingcapability.

It is a further aspect and objective of the VSI invention to provide ameans that the physical size of an individual processor module of anarray of processor modules that is largely independent of the size ofthe array of processor modules of which it is in, and withoutdiminishing the point-to-point communication capacity between theprocessor modules of the array of processor modules as the size of thearray of processor modules is increased.

DETAILED DESCRIPTION OF THE VSI INVENTION AND PREFERRED EMBODIMENTS

The preferred embodiment of the VSI invention is a method of integrationconsisting of fabricating a stack of Closely Coupled circuit layerswhere one or more of the circuit layers are not specifically designedfor a specific application or at least the intended application of thefinal VSI Component into which it is incorporated or fabricated. The VSIinvention enables the making of custom components comprising electronic,optical and or MEMS device layers solely from non-application specificdevice or circuit layers, or a combination of non-application specificand application specific circuit layers. Non-application specificcircuit or device layers or grouping of such device layers called a VSIdevice layer group may be generically referred to as VSI library devicelayers, wherein these VSI device layers or device layer groups ofcompleted physical circuit designs or fabricated circuits awaitsubsequent intermediate or final integration into a VSI component in theform of unfinished inventory. Such VSI library device layers are novelfrom the standpoint that they are completed physical designs and nofurther custom fabrication processing is necessary in order for them tobe fabricated into a VSI component with a custom or application specificuse; wherein the custom nature of the circuit is derived in part orwhole from the choice and quantity of the VSI library device layersselected for an intended application and these selected VSI librarylayers require no further application specific or custom fabricationtooling or processing in order to be used. Further, the VSI inventioncan also be comprised of all application specific device or circuitlayers without limitation.

The VSI invention can also be implemented as one circuit layer bondedface down onto a substrate wherein the substrate is limited to passivecircuitry on its surface and or has no circuitry and is intended to actas a heat sink or both or is intended to act primarily as a supportingsubstrate to the circuit layer. The circuit layer bonded to thesubstrate is thinned and vertical interconnections are formed from theface surface or top surface to the backside of the thinned circuitlayer. The vertical interconnections are then used to connect additionalcircuitry such as I/O drivers or ESD isolation that may be fabricated onthe backside and or I/O bond or contact pads.

The VSI invention enables greater integration into one die or componentthan is possible with planar ICs using current sub 0.15 μm lithographicprocesses, however, the use of this level of integration is onlypractical if the VSI component yields are economic, and by presentconsumer market driven standards this means a yield of at least 75% andhigher. The VSI invention enables high component yields through the samemeans as it enables arbitrary levels of integration, and this is to usethe increased level of interconnection capability to incorporatereconfiguration circuitry and test or ATE [Automatic Test Equipment]circuitry. There is also the additional unique aspect of VSI yieldenhancement and not possible with planar circuitry, this is that largeVSI circuits derive their cost effectiveness from the observation thatthe incremental cost in circuit layer area for reconfiguration controland test or ATE circuitry is more than offset by the reduction in costsof separate testing of numerous planar circuits of VSI circuitequivalents, reduction in the number of sophisticated I/O intensivepackages required for the packaged planar circuit equivalent of the VSIcircuit layers, reduced power dissipation resulting from the significantreduction in inter package I/O drivers and increased net performance dueto the reduced interconnection lengths for VSI circuit layers. A furtherobservation of the integration progression that uniquely benefits theVSI invention is that present IC manufacturing processes continue toreduce IC circuitry costs as a percentage of a finished packaged planarIC cost such that IC circuitry is now less than the combined costs ofpackaging and testing of the IC circuitry. These aspects of the VSIinvention are made clear with the example of a VSI component of 20circuit layers where four of these layers are reconfiguration and ATEcircuitry, wherein a 25% increase in the cost of IC circuitry is offsetby a 93.5% reduction in packaging and testing costs, resulting in a netfinished IC cost reduction of approximately 20%; wherein the cost ofpackaging and testing 16 planar circuits is reduced to the cost ofpackaging and testing one VSI IC and assuming that IC circuitry cost isapproximately 50% of a finished packaged planar IC.

The VSI invention further enables the incorporation of ATE andreconfiguration circuitry as circuit layers; wherein the reconfigurationcircuitry is used to alter the connections between portions of one ormore circuit layers and prevent their use as a result of testing thatdetermines the presents of a defect in said portions of circuitry. Thesegregated application circuitry of the VSI invention enables thesecircuit layers to achieve higher levels of utilization of the ATE and orreconfiguration circuitry without consideration of the number ofapplication circuit layers due to the ability to design in a highdensity of fine grain vertical interconnections wherein the physicalplacement and small layout area or foot print of the verticalinterconnections can be implemented without affecting the design orlayout of VSI circuit layers per application usage. There are twoprimary VSI capabilities that support this result. First the allocationareas for placement of vertical interconnection can be an initialcondition of the physical layout of a circuit layer. Secondly, the VSIinvention enables the backside fabrication of horizontal interconnectionwith conventional IC fabrication means, and therefore, verticalinterconnections that do not align from one circuit layer to the nextcan be routed to compensate for a misalignment; this may be the casewhere there is the intention to reuse a circuit layer designed for aprior VSI application or a second library comprising completed physicaldesigns or fabricated VSI IP [Intellectual Property] circuit layers.

The VSI invention can take a wide range of substrate stackingorganizations of electronic, optical and MEMS circuit and device layers.FIGS. 2 through 7 show by example a range of VSI component organizationsconsisting of two layers up to tens of layers. FIG. 2A shows a minimalVSI component consisting of two bonded substrates 1, 3, an activeelectronic circuit layer 1 face down bonded with a hermetic seal 2 ontoan active, passive electronic or optical circuit layer or a MEMS devicelayer 3. The lower substrate 3 may also act as a mechanical support andor for thermal dissipation and made from materials such as graphite,Boron Nitride, Aluminum or quartz. The bond 2 between the substrates ifmade from a process such as a metal thermal diffusion will form ahermetic seal, which may be necessary in certain applications, such asin the case when the lower substrate is an optical circuit layer or MEMSdevice.

A more complex example of the VSI invention is shown in FIG. 2B which isa cross section of a stack of three VSI circuit or device layers 5, 6,7. A first layer 5 with passive electronic elements on its top sidewhich is bonded face down or top side down onto the back side of thesecond layer 6 which is sufficiently thin to allow fine grain verticalinterconnections to be formed through the layer 6, and which is bondedface down or top side down onto the top side of the third layer 7. Bonds8 and 9 between the three layers may be hermetic seals depending on thebond process used. There are no VSI process limitations of what type ofcircuitry or devices that may be on a layer, for example, the secondlayer 6 can be an electronic or optical circuit layer with activedevices and the third layer 7 can be a passive or active electronic oroptical circuit layer, a MEMS device layer or serve a completelymechanical support or thermal dissipation function.

FIG. 3 shows a pictorial view of a VSI component or IC comprisingvarious application specific and non-application specific circuit layersof EEPROM circuit layers 10, MEMS device layer 12 such as a Rf antenna,CMOS logic and μP circuit layers 14, optical circuit layers 15, bipolarpower circuit layer 18 and conventional external I/O contact 11 pads;various organized internal vertical interconnections with standardizedand non-standardized protocol buses are not shown. FIG. 4 shows apictorial view of a VSI component or IC comprising all non-applicationspecific circuit layers of non-volatile memory circuit layers 20, DRAMcircuit layers 22, FPGA circuit layers 24, configuration and ATE or testcircuit layers 26, optical transceiver layers 28 and conventionalexternal I/O contact 21 pads; various organized internal verticalinterconnections with standardized and non-standardized protocol busesare not shown. FIG. 5 shows a pictorial view of a VSI componentcomprising a group 30 of memory circuit layers of several Gbits, a group32 of microprocessor layers comprising various types, an ATE andreconfiguration 34 circuit layer, a group 36 of FPGA circuit layers,various power regulation and Rf function 38 circuit layer andconventional external I/O contact 31 pads; various organized internalvertical interconnections with standardized and non-standardizedprotocol buses are not shown.

FIG. 3 and FIG. 4 show self packaged VSI component dice with totalthickness of approximately 200 μm and size or area of 50 mm²; the diedimensions or layer structures do not imply limitations on components ofthe VSI invention. The fine grain vertical interconnections and busingbetween the layers of these VSI components are not shown, however, crosssectional views of such component layers are shown in other figuresherein. Both of these figures use inorganic dielectric or metal thermaldiffusion bonding between each layer forming a hermetic seal of thedevice surfaces of the layers, and therefore, no additional packaging isrequired such that these VSI components demonstrate the self packagingaspect of the VSI invention.

FIG. 5 shows a self packaged VSI component of conventional planar die ICthickness of less than 500 μm and wherein the memory circuit layer groupis not application specific and microprocessor and FPGA circuit layergroups are application specific for operation in a consumer productproviding general personal computing capability and internet wirelesscommunications. This VSI component also has internal ATE self testcircuitry and sufficient redundant circuitry in fine grain and macrocircuit form such that in conjunction with the reconfigurationcircuitry, a net circuit yield of greater than 80% is enabled.

FIG. 6 shows in cross-section various groupings of layer types of a VSIcomponent. The purpose of this figure is to show the VSI invention canintegrate the variety of electronic, optical and MEMS technologies witha common process of substrate alignment, bond and thinning asappropriate wherein the preferred method of bonding is thermalcompression bonding but may include other bond means and the alignmentprecision is less than ±1 μm and preferably less than ±500 nm. The layergroupings are also significant due to the reuse capability of certainVSI circuit layers or groups. Layer group 6 c consists of applicationspecific optical circuit layers 66 in combination with a MEMS devicelayer 67 to form a portion of an optical communication switch. The otherlayer groups 6 a and 6 b may not be application specific, but selectedfrom broad non-application specific reusable inventory circuit layersfabricated prior to the initiation of the design of the VSI component ofFIG. 6. Circuit layer group 6 a consists of subgroups of one or morecircuit layers of programmable circuit layers 61, IP 62 and programmablerouting interconnections 63. Circuit layer group 6 b consists ofsubgroups of one or more circuit layers of memory 64 and test andreconfiguration logic 65. Not shown but assumed are multiple verticalbuses which interconnect one or more layer groups or subgroups and havestandardized placements or where placement variances are compensated forby horizontal routing formed by conventional fabrication techniques onthe backside of certain circuit layers. FIG. 6 shows a level ofelectronic, optical and MEMS integration that is not possible withpresent techniques or technologies. It should also be noted that thereis not a planar circuit equivalent for the VSI IC component of FIG. 6for the fundamental reason that the total circuit area of all of theelectronic circuit layers exceed the maximum lithographic circuitfabrication size of planar ICs.

The 6 a, 6 b circuit layer groupings of FIG. 6 may be placed in reverseorder and or one or both of these groupings maybe used more than once inthe VSI circuit stack to increase the capacity of the IC as needed.Further, the quantities of circuit layers within each of these groupingsmay also vary.

FIG. 7A is the cross-sectional view of several VSI component layerswherein two of the layers 71 a and 71 b have internal cavities 72 a, 72b. The cavities are supported at the edge of the VSI component die bydepositions of either dielectric and or metal 73 a, 73 b, a portion 73 aof which is shown between two overlying VSI components and would be ofsufficient width to accommodate the area commonly called the dicingscribe lane 79 where a cut in the VSI substrate stack is made whenseparating the VSI components or ICs from the substrate stack. The firstcircuit layer 71 a with an internal cavity shown as an optical circuitlayer or MEMS device layer to accommodate the structural features of thelayer. The second circuit layer 71 b with an internal cavity is shown asan electronic circuit layer wherein the horizontal interconnectionlayers are free standing with a majority of the normally soliddielectric material removed and wherein vertical columns 74 which canact as vertical interconnections and or mechanical support of thecavity, and support for suspended horizontal interconnections 74 a.Vertical columns 74 may also act as a means for thermal dissipation fromthe electronic layer to thermal spreading layer not shown but part oflayer 71 a 1. The layer bonds 76 a and 76 b adjoining the internalcavities form hermetic seals to preserve the atmosphere of the internalcavities which may be vacuum or partial pressures of an inert gas or afluid and sealed at the time the bonds are formed. Additional circuitlayers or substrates 71 c through 71 g are also shown. This VSIcomponent once completed can be packaged or used without packaging. Freestanding horizontal antennas for Rf transmission and reception can alsobe formed in this or a similar manner.

The internal cavity 72 b with the free standing electronicinterconnections of FIG. 7A can be fabricated by selective etch removalof the dielectric that normally would be used to fabricated thehorizontal interconnections of the circuit layer 71 b, or by using amaterial in place of the dielectric material that may be more readilyremoved such as amorphous silicon. The objective of fabricating the freestanding interconnections on a circuit layer is to use a fluid such asair as the dielectric separating the free standing interconnection whichhas a dielectric constant of approximately 1, the lowest possibledielectric constant. The bonding of the face of a circuit layer withfree standing horizontal interconnections as part of a VSI IC preventssubsequent damage to these very fragile interconnections, and therefore,the integration of such a circuit layer into a VSI IC is compatible withthe VSI invention IC fabrication processing. It should be noted thatbackside processing of a circuit layer with free standinginterconnections 74 a is consistent with the backside processing of acircuit layer with dielectric supported interconnections.

FIG. 7B shows VSI IC circuit layers 7 b 5 with VSI ICs 7 b 1 bonded toand forming vertical interconnections at their bond interfaces 7 b 2, 7b 3. The I/O bond pads of the VSI IC are also shown 7 b 4. The bondinglayers above and below the bond interfaces 7 b 2, 7 b 3 of the VSI ICs 7b 1 are patterned in a manner as shown in FIG. 7C. The bonding layer 7 c3 of FIG. 7C is patterned with open areas 7 c 2 and metal contacts 7 c1. Vertical interconnections between circuit layers are formed when VSIcircuit layers with bonding layers patterned in mirror image are bondedtogether coupling the isolated metal contacts 7 c 1 of either bondinglayer forming vertical interconnections between the circuit layers.

VSI Bonded Die Assembly Circuit Layer

An aspect of the fabrication of a VSI circuit layer is that it can be anassembly of thinned die as shown in FIG. 7F where dice 7 f 1, 7 f 2 areshown as thinned to a thickness of less than 50 μm, or less than 25 μm,or less than 15 μm or as in an implementation using substrates withbarrier layers such as a SOI substrate to a thickness of less than 10μm. There are certain circumstances wherein the implementation of VSIcircuit layers are more cost effective when formed from an array of diebonded onto a substrate or wafer than from a single substrate or waferwhereon an array of ICs or circuitry is fabricated; an example of such apossible circumstance could be where substrate sizes are not compatiblefor stacking.

A VSI circuit layer can be formed from a plurality of die 7 d 1, 7 d 2,7 d 3, 7 d 4 in FIG. 7D aligned and bonded face down across an array ofcircuit positions formed on a substrate or wafer or VSI wafer stack 7 f3. There may be one or more die aligned and bonded to a given circuitposition of the array of circuit positions on the substrate or wafer andthese die may vary in size and substrate material or fabricationprocess. The die bonded onto the substrate or wafer are aligned so thatvertical interconnections preferably can be formed with the substrate orwafer to the die as part of the bonding process, although such verticalinterconnections to underlying VSI circuit layers 7 f 3 can also beformed through the backside of the bonded die subsequent to completionof the thinning of the die array assembly; the preferred bondingprocessing is thermal diffusion bonding implemented with the use of oneor more of a number of possible materials as described herein, but it isnot limited to this process and could be accomplished with currentlyavailable non-metal bonding methods. The bond interface 7 d 8 bondingthe substrate or wafer 7 d 7 with a bonding layer 7 d 6 and a die 7 d 2with the bonding layer 7 d 5 of the die is preferably formed withpatterned bonding layers 7 d 6, 7 d 5 on the surfaces of the substrateor wafer and die 7 d 2. Such deposited bond layers 7 d 6, 7 d 5 aretypically less than 2 μm thick and can be thinner than 5,000 Å. The dice7 d 1, 7 d 2, 7 d 3, 7 d 4 when first bonded to the substrate or wafermay vary in thickness having thickness values in a nominal range of 100μm to 600 μm, typical for die cut from a wafer.

FIG. 7E shows bonded die on a substrate or wafer including a conformaldeposition of low stress or a controlled stress dielectric 7 e 1material such as oxide and or nitride deposited over the surfacecomprising all of the die 7 e 3, 7 e 4 bonded on the surface and on theexposed surface areas of the substrate 7 e 5. This dielectric depositionpassivates each die at its edges 7 e 2 of the bond contact from theaccumulation of particles and contamination or chemical attack duringsubsequent thinning processing steps. The dielectric may be deposited asone layer or in multiple layers and is preferably deposited to athickness that is approximately or slightly greater than the finaldesired thickness for the die assembly 7 e 3, 7 e 4 circuit layernominally by one or more microns. The objective is to deposit asufficient thickness of dielectric so that the deposited dielectricforms part of a continuous flat surface 7 f 4 with the backside of alldice 7 f 1, 7 f 2 after they are thinned as shown in FIG. 7F. Thisenables the use of subsequent conventional IC processing steps such asdielectric and metal deposition, RIE and lithography which are necessaryfor addition of more circuit layers or to form termination bonding padsfor I/O contacts for example.

The thinning of the bonded die is preferably done by first grindinguntil the bonded dice 7 f 1, 7 f 2 are level with the depositeddielectric 7 f 4, thereafter, substrate or wafer polishing, CMP or RIEprocessing used singularly or in combination can be used to bring thethickness of the die layer assembly 7 f 5 to the desired finalthickness.

The approach to using wafer polishing, CMP and RIE processing techniquescan depend upon hardness of the dielectric versus the substrate of thebonded dice. If there is a significant difference in hardness betweenthese materials, then dishing of one material versus the other canoccur. This can be avoided for example by adjusting the hardness of thedielectric or in the case where the dielectric is harder than thesubstrate of the dice, by uniformly selectively etching the dielectric 7f 4 through one of the available wet or dry etch processes a few micronsor fractions of a micron so it is below the surface of the dice causingthe backside of the dice to be above the level of the dielectric so thatthe dice subsequently can selectively be made planar with and thinned tothe thickness of the dielectric by such means as CMP.

The dielectric 7 e 1 is deposited onto the die following bonding of allof the die and prior to any die thinning processing is the preferredembodiment, because to do so after some amount of thinning of the diewill increase difficulty in cleaning the areas between the die fromaccumulated particles and will leave the areas between the dieunprotected from mechanical or chemical affects of the thinningprocessing methods used. Once the dice have been thinned to the level ofthe dielectric, measurement of the remaining thickness of the die canalso be more easily made by measuring the thickness of the dielectric inthe areas between the dice 7 f 4, since the dielectric does not have anyintervening layers that could possibly complicate or prevent simplerthickness measurements. Further, since the original deposition thicknessof the dielectric is known it can be monitored for a change in thicknessindicating that the final desired thickness of the VSI die assemblycircuit layer is being approached.

The deposited dielectric as a filler 7 f 4 in the areas between thebonded die is more cost effective than using a stenciled material suchas another substrate which would be bonded before or after the bondingof the die array assembly. Dielectric in the areas between the bondeddie also enables a simpler fabrication of vertical interconnections tothe VSI circuit layers below the die assembly layer. VSI circuit layersbelow the VSI die array assembly layer also can be a VSI die arrayassembly layer. A VSI die assembly layer can be any layer in a VSI waferstack and any number of them can be used in a VSI wafer stack. The diceused in a VSI die array assembly layer can be themselves VSI die; thisis worth noting because it enables the inclusion of previouslyfabricated VSI ICs such as those from a VSI physical wafer or substratecircuit library that were designed for the expressed purpose ofsystematic inclusion as either circuit wafer or substrate componentsduring the fabrication of a wafer stack or as singulated die componentsto be assembled as a VSI die array assembly layer.

It is also an aspect of the invention that the VSI die assembly circuitlayer be fabricated on a substrate or wafer consisting only of aninterconnect structure fabricated from one or more layers of metal anddielectric materials forming horizontal interconnections and overlying arelease layer as described in U.S. Pat. Nos. 5,354,695 and 5,915,167 andincorporated herein by reference. The substrate or wafer on which theinterconnect structure is fabricated can be a sacrificial substrate orwafer should a parting layer not be used, wherein the sacrificialsubstrate or wafer is sacrificed subsequent to the bonding of the VSIdie assembly circuit layer onto a VSI circuit stack. Further, aprincipal purpose of the interconnect structure of the substrate orwafer that the dice will be bonded is to provide alignment marks for thealigning the dice onto the substrate or wafer during bonding, however,it is not necessary that an interconnection structure be fabricated, butit is necessary that at least the alignment marks be fabricated on thesubstrate or wafer to effect accurate positioning of the die to bebonded. In this aspect of the invention VSI die assembly circuit layersthat are fabricated upon a separate substrate or wafer can be reservedor inventoried for subsequent VSI stacking fabrication as part of aphysical VSI circuit layer design library. One example of this aspect ofa VSI die assembly circuit layer is quartz substrate upon which arelease layer and interconnection structure are fabricated throughconventional IC fabrication means, and subsequently, die are bonded andthinned as described herein to form a VSI circuit layer that can beincorporated into a VSI circuit stack at a time when needed and thequartz substrate once released can be reused.

First Preferred Embodiment of the VSI Invention

A first preferred embodiment fabrication method and the devices thatresult from this fabrication method of the VSI invention is whereinClosely Coupled electronic, optical or MEMS device layers used to form asingle integrated device of die form and further each layer used in thefabrication of the Closely Coupled device layers were themselvesoriginally fabricated as non-application specific with respect to thefinal VSI device in which they were applied. It is an importantdistinction of this first embodiment that the circuit or device layersused were initially designed with the expectation of being used to forma VSI component, and therefore, each circuit or device layer is designedwith the same die or foot print dimensions and conventions for verticalinterconnections or busing between various layers are also a part ofeach circuit or device design, however, the hardwired or physicalfunction of each such circuit or device layer is not designed inanticipation for use in a specific VSI component application.

The resulting VSI component of this first preferred embodiment of theVSI invention allows the VSI component to be fabricated from a libraryof completed physical circuit designs and or previously fabricatedcircuit or device substrates which can also be referred to as aninventory of circuit or device substrates that will have a usefulinventory life time that may be greater than anyone VSI component or VSIIC for which these substrates are used. This aspect of the capability ofthe VSI invention is novel for it allows for the first time thefabrication of a planar circuit or IP [Intellectual Property] to beseparate from its eventual fabrication in a larger integrated circuitstructure. This means that the design, circuit simulation, fabricationtooling set and inventory life time of a fabricated planar [IP] circuitor device layer can be fixed quantities and need not require theirobsolescence and recreation for each application design use. Thisfurther means that for the more frequent event of design updates orenhancements to an integrated circuit application, that all planarcircuits [IP] not physically affect by such will not result in theobsolescence of planar circuit inventory and recreation of a fabricationtooling set for that planar circuit.

VSI library or inventory of completed physical circuit designs and orfabricated circuit layers of the first preferred embodiment of the VSIinvention may be a group of circuit layers wherein such layers haveinterdependent designs. The design of such layers does not necessaryaffect their use as non-application specific library layers for thereason that the use of the group of layers still has a non-applicationspecific range of use. Examples of such groups of VSI layers arememories [DRAM, EEPROM, MRAM] and FPGAs.

The first preferred embodiment of the VSI invention enables thefabrication of an application specific integrated circuit with varyingamounts of logic processing capability such as a varying number of μPs,DSPs or IP, varying amounts of volatile and or non-volatile memory orother distinct memory type such as CAM [Content Addressable Memory], andother capabilities such as optical transceivers or MEMS mass storagewithout the present and unavoidable requirement of current ICmanufacturing to create a new design and layout of the competeintegrated circuit, perform circuit simulation and fabricate tooling forthe IC and then fabricate the IC. This first preferred embodiment issimilar to the well established method of PCB assembly, however, withoutthe well known limitations in that art regarding planar IC packaging,package I/O count, I/O power requirements, I/O signal delay andindividual testing of the planar ICs of the PCB prior to the functionaltesting of the completed PCB. The first preferred embodiment of the VSIinvention enables the fabrication of application specific integratedcircuits without unique circuit design engineering efforts or uniquecircuit fabrication tooling.

This first preferred embodiment of the VSI invention may include the useof backside device and interconnection fabrication of Closely Coupledcircuit or device layers. Back side processing is used as a means forhardwired circuit corrections of circuit defects to achieve circuityield enhancement; the implementation of specific logic functions orapplication specific logic functions; and, interconnection routing whereby the bonding pattern used to form vertical interconnections betweenlayers is modified to achieve a specific interconnection designobjective or horizontal backside interconnections are modified as ameans to achieve a specific routing use of an existing verticalinterconnection bonding pattern. The wiring patterns for verticalinterconnections of VSI circuit layers are subject to change or theremay be several vertical interconnection [bussing] conventions sometimesreferred to as interconnection standards, and therefore, existing orinventory VSI circuit layers that are affected by such verticalinterconnection differences can avoid obsolescence or have a greaterrange of application usage with back side interconnection processingchanges that bring vertical connection contact patterns of such VSIcircuit layers into compliance with the vertical interconnectionconventions of the VSI component on which they are being integrated.

This first preferred embodiment of the VSI invention may include the useof through the substrate alignment processes that enable alignmentaccuracies of less than ±1 μm for the alignment of circuit substratesand or Closely Coupled circuit, device layers when fabricating a VSIcomponent. The greater the alignment precision of the method used toalign the VSI component layers, the greater the level of layer to layercircuit integration density is possible in terms of verticalinterconnection density and electronic and optical circuit elementcoupling.

This first preferred embodiment of the VSI invention may includereconfiguration control circuitry used to reconfigure circuitry on oneor more other layers of a VSI component and further described herein.This circuitry may exist segregated to a circuit layer or may beintegrated with other functions of a circuit layer. The reconfigurationcircuitry performs at least two principle functions: first, enabling ordisabling the use of some portion of circuitry, and second, enabling howthat same portion of circuitry will be used. The reconfiguration controlcircuitry is enabled through conventional circuit or device means and isinterconnected to the circuitry it effects through the fine grainvertical interconnections of the VSI invention.

This first preferred embodiment of the VSI invention may includeinternal self test circuitry or ATE [Automatic Test Equipment] circuitryused for testing circuitry on one or more circuit layers of a VSIcomponent. The ATE test circuitry is differentiated from internal selftest circuitry by the distinction that ATE circuitry is programmable foruse over a wide range of electronic and optical circuit types; theinclusion of ATE circuitry capable of being programmed to perform afunctional test of all or a portion of an IC is unique to the VSIinvention and the inclusion of ATE circuitry is enabled through the finegrain vertical interconnections of the VSI invention. The self testcircuitry may exist segregated to a circuit layer or may be integratedwith other functions of a circuit layer. The ATE circuitry preferablyexists segregated to one or more circuit layers. The self test circuitryor ATE circuitry can be programmed for performing tests from an externalor internal source. If self test and ATE circuitry are both present, theself test circuitry preferably can be coordinated in its use by the ATEcircuitry. The self test or ATE circuitry, if reconfiguration circuitryis present, is preferably used to determine what circuit defects existin the reconfiguration circuitry and then in conjunction with thereconfiguration circuitry, various or all portions of the circuitry onother VSI component layers. If reconfiguration circuitry is notcompletely internal to the VSI component, circuit defects may beisolated from use by external control circuitry that implementinterconnection changes such as through the use of fuses or anti-fusesthat prevent the use of the portion of a VSI layer with the defect orthe whole VSI layer. There may be multiple self test circuits with theintended purposes of providing redundancy should the self test circuititself be defective, providing application specific test functions suchas those tests specific to memory or logic, optical circuit elements andMEMS layers. It is a preferred aspect of the VSI invention thatsufficient internal self test circuitry or ATE circuitry be present suchthat the VSI component is capable of performing all circuit testingrequired during circuit burn-in processing without the presence ofexternal testing equipment. It is also a preferred aspect of the VSIinvention that the VSI component is capable of performing sufficientcircuit testing during its useful life in order to determine if acircuit defect is present in either a dynamic or static testing meansand to use this information in conjunction with reconfigurationcircuitry of the VSI component to avoid the use of defective circuitrywith the objective of extending the useful life of the VSI component andavoiding the necessity for physical replacement of the VSI componentwherein such efforts may exceed the cost of the VSI component. Theinclusion of ATE circuitry into the VSI stack has several further uniqueadvantages such as the capability to match the fabrication technology ofthe ATE circuitry to the circuitry under test, to perform extended atspeed testing for extended periods of time sufficient to determine testcoverage approaching or achieving 100% of circuit function, providing ameans to determine circuit yields prior to the dicing of the VSI stackinto separate die, and to make IC testing transparent to IC design andmanufacturing processes. The incorporation of self testing circuitry andor ATE circuitry in combination with the VSI invention enables fullfunctional testing of ICs to be performed in wafer or die form duringburn-in processing.

This first preferred embodiment of the VSI invention enables it to beused as a predefined electronic, optical and or MEMS architectureproviding a platform for the subsequent development of other hardwareplatforms. The term platform is presently used to describe a known towork hardware system or subsystem electronic architecture of busing,processors, memory, peripheral and IP [Intellectual Property] blocksimplemented as one or a few planar ICs from which in combination withsoftware an expected range of various application products can rapidlybe designed and developed. Such planar IC platforms also incorporatevarious EDA [Electronic Design Automation] tools for theirimplementation. The limitation that is known to exist with this platformapproach to product or application development is that the definedenvelope of the architecture does not anticipate all future applicationrequirements and cannot be easily changed once developed as planar ICswith respect to its initial platform design due to the level of designeffort results in changes to many hardware functions and or thelimitations of the EDA tools that accompanied the platform. Functionalenhancements to a platform made with planar ICs does not easilyaccommodate a requirement to add additional hardware functions such asmicroprocessor units or IPs. The VSI invention enables the developmentof hardware platforms that can be enhanced with electronic, optical andMEMS hardware functions through the addition of VSI layers with thedesired hardware function. An objective of present planar IC hardwaredesign platform is the ability to reuse a designed hardware function ina series of product applications with only a minimum redesign effortrequired of the hardware function for achieving its reuse; often this isnot the case because the placement and routing demands that result fromplanar IC design. The VSI invention enables the insertion or removal ofhardware functions implemented as a VSI circuit layer without requiringredesign or change of hardware function prior to its subsequentinsertion into a VSI application specific platform or product stack. TheVSI invention further enables the expectation that design changes can belimited to only vertical interconnection routing changes on circuitbacksides in order to integrate a desired hardware function into aplatform or platform derived application end user product. VSI hardwareplatforms are uniquely enabled due the VSI inventions capability to addor remove hardware function device layers without affecting the designor implementation of the other device layers in the VSI platform stack.This capability for adding or removing hardware functions as device orcircuit layers also eliminates the development requirement in planar ICsto use various EDA tools to effect the addition of a hardware functionor what is often referred to as architectural tuning; wherein the layoutof the planar IC is incrementally adjusted to achieve circuit timingclosure. Timing closure of a planar circuit nominally requires theeffective shortening of horizontal interconnections between hardwarefunctions by hundreds to thousands of microns in length, by signalamplification or slower operation of the IC, the thickness of VSIcircuit layers which are nominally less than 25 μm eliminate thepossibility that the distance between hardware functions on any two VSIcircuit layers will result in a timing closure failure.

This first preferred embodiment of the VSI invention may include the useof self packaging. The self packaging aspect of the VSI inventionresults from the bonding of all Closely Coupled circuit layers of a VSIcomponent wherein as a result of such bonding the circuitry of allcircuit layers is internal to the VSI component and cannot be damaged bymechanical means. Further, if the bond process used for bonding thelayers of a VSI component form a hermetic seal, then the VSI componentis also hermetically sealed.

Second Preferred Embodiment of VSI Invention

A second preferred embodiment of the VSI invention is the fabricationmethod of the first embodiment but wherein one or more but not all ofthe planar circuits or IPs for use as VSI circuit layers are designedfor one or more specific applications of a VSI component. This alsoincludes the application specific design of circuitry on the backside ofone or more of the Closely Coupled circuit layers whether or not the topside planar circuit is of an application specific design for a VSIcomponent.

Third Preferred Embodiment of the VSI Invention

A third preferred embodiment of the VSI invention is the fabricationmethod of the first embodiment but wherein all of the planar circuits orIPs for use as VSI circuit layers are designed for one or more specificapplications of a VSI component. This third preferred embodiment of theVSI invention is most closely related to what is presently called anASIC [Application Specific IC] for the reason that all of the VSIcircuit layers are designed for a specific application or set of welldefined applications. It can also be said that this third embodiment ofthe VSI invention is related to all production ICs no matter what theintended volume production whether only a few IC parts are fabricated ora high volume of parts are repeatedly fabricated as in the case ofembedded microprocessors or the microprocessors used in PersonalComputers.

Additional Considerations of the Preferred Embodiment of the VSIInvention

Further, it is a well know that circuit yield is related to the size ofa circuit, and therefore, the greater number of layers in a VSI circuitor component, then the lower the expected yield VSI Component. Yieldenhancement is a principle characteristic of the VSI invention. Theyield enhancement of a VSI Component is implemented by fine grainvertical interconnections used to enable, disable or power circuitdevices, groups of circuit devices or circuit blocks, or whole circuitlayers by yield enhancement circuitry located on a different circuitlayer of the VSI Component or external to the VSI Component. Theseparation of the yield enhancement circuitry to separate circuit layersallows the enhancement circuitry to be designed and fabricated withoutaffecting the design, fabrication and quantity used of other circuitlayers in a VSI Component.

VSI Process Methods

The preferred embodiment of the VSI fabrication process method forms astacked integrated circuit of closely coupled circuit layers andcomprising:

-   -   1. Two or more non-application specific or application specific        circuit layers, or one or more non-application specific or        application specific circuit layers and one or more MEMS layers        with vertical data rate transfers equivalent to on circuit or on        chip horizontal data rate transfers of planar ICs.    -   2. Internal or external yield management circuitry with internal        yield enhancement configuration circuitry.    -   3. Interconnection and or device fabrication on the backside of        a circuit layer substrate.    -   4. One or more layers requiring layer to layer alignment of less        than ±1 μm, less than ±500 nm and less than ±250 nm.

VSI Substrate Back Side Interconnection

The VSI invention increases interconnect density by enabling an equalamount of horizontal interconnect layers to be fabricated on thebackside of a thinned semiconductor IC substrate as presently possibleon the front side of the IC substrate. This 2× improvement overconventional interconnection routing density is enabled with the use ofconventional interconnection fabrication methods once the semiconductorportion of the IC substrate is sufficiently thinned to a thickness ofless than 50 μm and preferably in a range of 0.5 μm to 10 μm for bulksubstrates and in a range of 0.010 μm to 10 μm for SOI substrates; theseranges are approximate and not to be considered limitations on theactual thickness that can be achieved. The thinning of the substrate isrequired to enable low cost vertical interconnect or via fabricationfrom the front side of the substrate to the back side. The thinning ofthe substrate or partial thinning can occur before or after bonding ofthe IC substrate as part of a VSI circuit stack. The IC substratethinning step is independent of whether it is bonded to a supportingsubstrate such as a VSI circuit stack if the IC substrate is fabricatedwith stress controlled dielectric or low stress dielectric materialssuch that the net stress on the surface of the substrate prior tothinning is less than 8×10⁸ dynes/cm² [80 Mpa] in accordance with theinventor's U.S. Pat. No. 5,354,695.

The capability for fabrication of similar horizontal interconnectdensities on either side of VSI circuit layers enables the a doubling ofsemiconductor circuit device interconnection density without therequirement of additional geometry scaling of the interconnect [featuresize]. Conversely, this also allows the use of larger interconnectgeometries with the objective of lowering the number of critical highercost mask [feature size] layers, but achieving the same or a betterrouting interconnection density by completing the interconnect on theback side of the IC substrate. The ability to fabricate circuitstructures on the back side of an IC substrate is not limited tohorizontal interconnections but can also include such circuit structuresas back side gates [dual gates], passive circuit elements, circuitreferences or wave guides.

The VSI invention enables the fabrication or the completion offabrication of passive and active circuit elements or devices such asresistors, capacitors, inductors, transistors, floating gatetransistors, diodes, optical amplifiers, optical wave guides, etc.Backside circuit element fabrication is enabled as a result of the facedown bonding of wafer or substrate onto a VSI substrate stack. Thebackside of the just bonded substrate in now available for circuitfabrication, if the substrate already is of the desired thickness andsurface preparation. The substrate, if not already thinned to a desireddimension, is thinned by numerous known process methods and orcombinations of same such as grind and polish, plasma etch, RIE, spraywet etching or thinning to a existing barrier layer or etch stop. Oncethe backside of the just bonded substrate is of desired thickness andsurface preparation, most conventional IC fabrication processingtechniques can be used that do not exceed VSI stack temperature heatingbeyond the thermal budget limit of specific materials in the stack. Ifan inorganic bond material such as copper is used, a CMOS VSI stackprocessing temperature in a range up to 550° C. could be used. Repeatedprocess step heating of a CMOS VSI stack for example to temperaturesbeyond 600° C. can result in semiconductor auto-doping. However, suchhigh temperature steps as dopant annealing or activation, source/drainohmic contact formation or thermal oxidation of silicon can be localizedto surface heating effects through the use of excimer laser processing.In the case of backside circuit element fabrication where a hightemperature step is required that is beyond the thermal budget of theVSI stack, high temperature surface effect processing which does notheat the lower portions of the VSI stack appreciably can be used toperform such processing. The use of surface effect high temperatureprocessing in combination with VSI backside processing enables thefabrication of most circuit elements or devices which are presentlylimited to fabrication on a first or top side of a planar circuitsubstrate.

The backside processing aspect of the VSI invention uniquely enables thefabrication of passive and active circuit elements and MEMS, on thebackside of completed circuit substrates or MEMS substrates with the useof conventional semiconductor fabrication equipment. This unique methodfor circuit or MEMS processing allows for the completion of circuitelements such as dual gate transistor with backside gates, or dualfunction circuit elements such as a combined transistor and memory cellcircuit element further described herein. Further, lower temperatureepitaxy deposition or semiconductor poly-crystallization processes incombination with the VSI backside processing enable the fabrication ofadditional semiconductor material layers for the fabrication ofadditional active circuit elements such as heterojunction transistors orTFTs [Thin Film Transistors].

VSI Backside Circuit Layer Process

The VSI invention enables the fabrication of interconnection on thebackside of a thinned semiconductor substrate or an appropriate carriersubstrate like a deposited dielectric such as silicon dioxide, or glassor quartz substrates which could be used in the fabrication of depositedsemiconductor circuit devices or elements such as polysilicontransistors. The VSI process method uses SOI substrates orheterojunction semiconductor substrates such as GaAs on Silicon orSilicon on Sapphire to provide a means to precisely terminate or stopthe thinning of the backside of such a semiconductor circuit substrate.The VSI process method uses a carrier substrate with a release layerunder the deposited semiconductor devices to remove the carriersubstrate.

The VSI process enables backside fabrication of electronic or opticalcircuit devices or elements following the bonding of a circuit substrateand the thinning of the substrate if and as required to allow theformation or completion of vertical interconnections from the frontsurface or bond layer of the last bonded substrate. The methods forfabrication of electronic or optical circuit devices are the same asthose presently used to fabricate such devices on a semiconductor orcarrier substrate. This is enabled by the VSI invention when preferablythermal diffusion bonding is used or inorganic bonding processes thatcan tolerate elevated temperatures from deposition or surface annealingprocesses by laser or rapid thermal processing.

The use of a dual SOI substrate is another embodiment of the VSIinvention for backside electronic and or optical circuit devicefabrication. FIG. 9 shows in cross-section a dual SOI substrate with atop or first device layer 91, an isolation buried layer 92, a bottom orsecond device layer 93 and a thin barrier dielectric layer 94 fortermination of the backside substrate thinning process. The two devicelayers 91 and 93 may have nominal thickness ranging from 50 Å to morethan 5,000 Å, the isolation layer 92 may have a thickness ranging fromapproximately 500 Å to 5,000 Å and the buried dielectric layer 94 mayhave a thickness of typically less than 500 Å and less than 150 Å. Thebarrier dielectric layer 94 provides a precision etch stop when thinningthe backside of the SOI semiconductor substrate, the etching process canbe terminated by the dielectric layer without etching any of the seconddevice layer 93.

The dual SOI substrate is made with conventional oxygen ion implantprocessing means except instead of only implanting one dielectric layer,this implementation of the VSI process requires the second burieddielectric layer 94, wherein the buried dielectric layer 94 is implantedfirst followed by the implant of the isolation dielectric layer 92. Thedual dielectric implant or buried layer structure in combination withthe VSI backside fabrication processing enables a single SOI substrateto be used for fabrication of two distinct layers of electronic oroptical devices. The use of other compound semiconductor substrates suchas GaAs on Silicon, or InP on Silicon allow the backside of the GaAs orInP semiconductor device layers to be used in a similar manner, however,without the requirement for a dielectric isolation layer because thesesemiconductor materials are semi-insulating, and therefore, have lowerintrinsic conductance. If the compound substrate is formed on a SOIsubstrate, the buried dielectric layer could be used to form a uniformcrystalline device layer on the backside of the substrate.

A primary advantage or benefit of the use of a VSI dual SOI substrate isthe reduction in substrate cost, wherein two active circuit layers canbe fabricated on one semiconductor substrate. It is also clear that thisadvantage is provided by compound semiconductor substrates like GaAs onSilicon, however, silicon is presently the most widely usedsemiconductor substrate material, and therefore, the use of the VSI dualSOI substrate is of unique cost advantage. Some of the unique benefitsof the VSI dual SOI substrate is the capability to fabricate a CMOScircuit layer where the NMOS devices of the CMOS layer are on one sideof the dielectric isolation layer 92 and PMOS of the CMOS devices are onthe opposite side; the same advantage can be used to achieve acomplementary Bipolar circuit layer.

VSI Enhanced Diffusion Bonding Processes

The VSI invention enhances metal thermal diffusion bonding of twosubstrates by combining the primary metal film with one or moresecondary metal films, preferably with lower melting temperatures thanthe primary metal film, with the objective of lowering the temperatureand or pressure necessary to achieve a desired bond quality. The use ofsuch secondary metal films also has the objective that with subsequenttemperature annealing the secondary metal films will diffuse into theprimary metal film resulting in a metal bond layer that has a higherworking temperature. The use of the term working temperature means atemperature wherein the physical characteristics of the resulting metallayer are compatible with subsequent fabrication processing steps andsufficient to meet the mechanical and electrical operating requirementsof the IC of which it is a part.

Examples of such multiple bonding metal films with copper [Cu] as theprimary film are Cu:Sn, Cu:Zn, Cu:Ni:Sn or Cu:Sn:In, but numerous othercombinations of metals are also possible such as Al:Sn. In such metalfilm systems the primary metal film would have a thickness of 2,500 Å to20,000 Å and a secondary films would have a thickness of typically lessthan 2,000 Å and preferably about 500 Å. The primary and secondary metalfilms are preferably deposited sequentially without exposure toatmosphere, such as in the case of sequential sputtering steps in thesame sputtering process tool. In this manner a metal oxide is notallowed to form on the surface of an underlying metal film. The metalfilms as first deposited have their purer form properties, so a properlychosen secondary film with a lower melting temperature and a high solidsolubility coefficient or diffusion rate for the primary metal willachieve two goals for enhanced VSI bonding: enable substrate bonding tooccur at a lower temperature, and, after subsequent lower temperaturethermal annealing of the bonded wafers, allows for the diffusion of thesecondary metal film into the primary film wherein the resulting metallayer of diffused metal films has a set of physical properties that moreclosely resemble those of the primary metal film such as a meltingtemperature that is higher than the melting temperature of the secondaryfilm, and therefore, a higher working temperature for the metal bondlayer resulting from the initial deposited metal films or other physicalproperties of the primary metal film.

A more explicit example would be a Cu:In set of metal films. The In toIn films will form a bond at less than 100° C. with applied mechanicalpressure, but the In will diffuse into the Cu metal films on either sideof the bonded In films with annealing temperatures in a range of 80° C.to 150° C. or higher wherein the resulting diffused metal film will havea melting temperature that is much greater than the melting temperatureof In at approximately 122° C. The resulting benefit of such a combinedmetal layer is one that retains the higher electrical and thermalconductivity of Cu without requiring the use of bonding temperatures inexcess of 350° C. that would be required to form a Cu to Cu bond in atimely manner and without the use of higher mechanical bond process steppressures.

VSI Process Method for Low Power High Bandwidth Data Transfer

The VSI invention enables through vertical integration of two or morecircuit layers a low power means for high bandwidth data transfer. Thetransfer rates through horizontal interconnect metallization on thesurface of a conventional IC such a microprocessor presently demonstrateinformation transfer rates in excess of 32 Gbytes/s. This example istaken from the transfer of information between microprocessor and cacheover a 256 bit wide bus with a 250 ps time interval and over signal buslines of 1 mm [1,000 μm] or greater in length.

Using similar information transfer circuitry over a shorter distance ofnominally 250 μm or less and a bus path width of 2,048 to 4,096 [thisbus path width is consistent with memory array sizes such as in DRAMs],the VSI invention enables a bandwidth transfer rate in excess of 2Tbytes/s between circuit layers. Conventional IC I/O circuit driver [ICto IC on a common PCB] transfer power is nominally 10 mWatts andgreater. The VSI power transfer per serial signal line between circuitlayers is nominally less than 1 μWatt. This results in a power transferdissipation reduction of approximately 1/10,000 less per I/O [verticalinterconnections] between VSI circuit layers.

VSI Process Method and Complexity Reduction

The VSI invention is a method for vertical integration of two closelycoupled circuit layers, or ICs which are bonded together in a face toface fashion, or a VSI circuit layer and a MEMS device layer. Thebonding method is preferably thermal diffusion bonding and the bondingprocess preferably forms a hermetic seal of the surfaces of the ICcircuit layers. A hermetic seal is formed when thermal diffusion bondprocessing is performed using inorganic metal or dielectric materials.Preferred bonding metals are metals such as Al, Cu, In, Sn, Zn, Ag, Au,and alloys of same. Preferred bonding dielectrics are oxides of siliconand nitrogen, and glasses with glass transition temperatures below 450°C. The circuit layers are interconnected by fine grain verticalinterconnections and these interconnections are organized to form atleast one bus path or connections for information transfer with a serialline data transfer rate capability of 100 Mbps and preferably greaterthan 500 Mbps or 1 Gbps, or 5 Gbps using conventional logic circuitrywith a vertical separation of typically less than 2 millimeters using nocircuitry of a design for transmitting signals distances greater than 10millimeters. The circuitry used for sending information between thecircuit layers on vertical interconnections does not requiretransmission line structure or specialized circuitry, this is due to theshort distance of the vertical interconnection which are nominally lessthan 250 μm, and therefore, nominally less than a majority of the longerhorizontal signal lines typical of a circuit layer or planar ICs ingeneral. The circuit drivers for external I/Os or off IC transmissionfor both circuit layers are preferably fabricated only as part of onecircuit layer. Such external I/O circuit drivers may be fabricated onthe backside of anyone of the circuit layers, and the external bond padsof the VSI IC are all formed on the backside of one or both of theexternal circuit layers.

The VSI invention enables the backside processing of a single circuitlayer by bonding a circuit substrate face down onto a second substratewithout active circuit elements which serves the purpose of providingsuch capabilities as mechanical support, thermal dissipation,interconnection structures and or passive circuit elements. This secondsubstrate may be made from a non-semiconductor material such as quartz,graphite, Boron Nitride, Aluminum, NiFe alloys or Mo. After the circuitlayer substrate or wafer is bonded to the second substrate it is thinnedas necessary, and thereafter, active circuit elements and horizontalinterconnections may be fabricated on the backside of the circuitsubstrate.

The use of the VSI invention with only one circuit layer is its minimalform, with a primary benefit of enabling access to the backside of acircuit layer whereupon conventional semiconductor fabrication processesmay be used to form or complete the formation of active circuit elementsor horizontal interconnections. An additional substrate may be bondedonto the backside of the circuit wafer in order to form a hermetic sealof the circuit layer's surface, to form a means of mechanical protectionof the circuit layer, and thereby, creating a package for the circuitlayer.

VSI Process Method and Yield Enhancement

The VSI invention is a method for vertical integration of two or moreclosely coupled circuit layers and one or more MEMS device layers. Thebonding method is preferably thermal diffusion bonding and the bondingprocess preferably forms a hermetic seal of the surfaces of the ICcircuit layers. A hermetic seal is formed when thermal diffusion bondprocessing is performed using inorganic metal or dielectric materials.Preferred bonding metals are metals such as Al, Cu, In, Sn, Zn, Ag, Au,and alloys of same. Preferred bonding dielectrics are oxides of siliconand nitrogen, and glasses with glass transition temperatures below 450°C. The circuit layers are interconnected by fine grain verticalinterconnections and these interconnections are organized to form atleast one bus path or connections for information transfer with a serialline data transfer rate capability of 100 Mbps and preferably greaterthan 500 Mbps or 1 Gbps, or 5 Gbps using conventional logic circuitrywith a vertical separation of typically less than 2 mm and withoutrequiring circuitry for transmitting signals distances greater than 10millimeters. The circuitry used for sending information between thecircuit layers on vertical interconnections does not requiretransmission line structure or specialized circuitry, this is due to theshort distance of the vertical interconnection which are nominally lessthan 250 μm, and therefore, nominally less than an majority of thelonger horizontal signal lines typical of the circuit layer or planarICs in general. The circuit drivers for external I/Os or off ICtransmission for both circuit layers are preferably fabricated only aspart of one circuit layer. Such external I/O circuit drivers may befabricated on the backside of anyone of the circuit layers with theexternal bond pads of the VSI IC formed on the backside of one or bothof the two external circuit layers.

Increasing the number of VSI layers will negatively affect the yield ofthe VSI component or IC in just the same manner as increasing the areaof a planar IC. The VSI invention enables yield enhancement through theuse of reconfiguration and or test layers. The fine grain verticalinterconnections enable the reconfiguration layers to change theinterconnection routing on one or more circuit layers when a portion ofa circuit layer is determined to be defective. The test circuit layercan be used to determine defective portions of a circuit layer. Testcircuitry can be physically external to the VSI component, but it is thepreferred embodiment that test circuitry be internal to the VSIcomponent to enable circuit reconfiguration on going during the usefullife of the VSI IC. The use of reconfiguration layers, wherein also aredundant reconfiguration circuit layer or a redundant reconfigurationlayer may be used to increase its yield, can be the primary yielddeterminate for the VSI component. This is a VSI yield factoring or VSIIC yield localization wherein the VSI IC yield is determined by alimited number of circuit layers of a VSI IC with a large number ofcircuit layers. VSI IC yield factoring is when VSI IC yield isdetermined primarily by the yield of its reconfiguration circuitry, orby the yield of a limited number of circuit layers which enable theyield of a VSI component to be largely determined by the designed use ofthese circuit layers, examples of VSI yield factor circuits are VSImemory components, VSI PLD components or large logic circuitry VSI ICswith appropriate redundant logic circuitry resources. The yield of VSIcomponents, therefore, can be independent of the total area of all ofthe circuit layers comprising the VSI component. Further, the yield ofan arbitrarily large VSI component or IC can be designed to always havea yield greater than 80%.

The VSI invention enables the fabrication of a circuit layer or a groupof circuit layers with a well known yield expectation and wherein theirsubsequent inclusion in a completed VSI component affects the final VSIIC yield in a predictable and calculable manner that can be determinedprior to VSI component fabrication. For example a memory circuit layergroup, processor circuit layer group and a FPGA circuit layer group eachwith their own yield enhancement circuitry can be combined into a VSIcomponent wherein the yield of the VSI component is determined in partby the known yield of each group and not the yield that would beanticipated by independently considering the yield of each circuit layerof the VSI component.

The VSI invention enables the use of 100% circuit redundancy for anycircuit type without consideration to the layout of the circuit. Theapplication of full redundancy in planar circuits is limited by the needto provide additional horizontal interconnection routing for redundantcircuit sections and a doubling of die size which restricts the area ofa planar circuit prior to redundancy circuitry additions toapproximately one half the reticle area of present lithography toolwhich is for most lithography tools less than 3 cm². The VSI inventiondoes not have either of these limitations. The VSI full redundancymethod stacks circuit layers of identical of mirror image layouts thatare divided into arbitrary blocks of circuitry that can be isolatedthrough the use of fuse links or by pass transistors if the block isfound defective. If a block is found defective, it is isolated and thevertically positioned redundant or spare equivalent circuit block isused. Since both the first block and its redundant spare are verticallyposition relative to each other there are not routing delay effectsinduced because the routing length to each block are identical or nearlyso. Further, the full reticle of the lithography tool can be usedbecause no planar area need be used for placement of redundantcircuitry. And most importantly, the yield of the circuit is improvedfor the well established reason that whatever the number of partitionedfully redundant blocks in the circuit, yield product of their separateyields will always be higher than the yield of the circuit taken for aplanar circuit. For example, a planar circuit of size 4 cm² in astate-of-the-art technology can be expected to have a yield of less than25%, whereas the same circuit as a fully redundant VSI IC of eightblocks each with an area of approximately 0.5 cm² and an approximateyield of 85% would have a VSI circuit yield of approximately 83% or[1−[1−0.85]²]⁸. It should be clear that the VSI yield calculationimproves with a greater partitioning and is applicable to all planarcircuits regardless of physical area if the effective yield cost is lessthan 50% after inclusion of test and packaging cost which is the casefor many state of the art high performance logic circuits, and 32 bitand 64 bit microprocessors with die sizes greater than 2 cm². This VSImethod of yield enhancement also can be extended for use with any numberof circuit layers or more than one redundant spare circuit block. Anadditional advantage of this VSI redundancy method is the design andlayout of a circuit layer is much the same as would be the case for aplanar circuit but for the incorporation of isolation circuitryassociated with each redundant block.

The VSI invention enables yield enhancement by allowing IC processes tobe segmented to separate circuit layers of the VSI component. This isdistinct from the segmentation by circuit layer of semiconductortechnologies such as the use of CMOS on one circuit layer and GaAs, GaN,InP, InSb, or ZnTe on other circuit layers. It is often the case that inthe design of large CMOS planar ICs that only a limited portion of theIC requires the use of the most advanced IC process fabricationtechnology, whereas, the remaining and generally larger portion of thecircuit does not. The more advanced IC process will have a lower yieldper area than a less advanced process. The result is a reduced yield ofthe planar IC due to the use of a more advanced IC process over a largerIC area. The VSI invention enables that portion of the planar ICrequiring the more advanced IC process to be fabricated as a separatecircuit layer and the remaining portion of the circuit to be fabricatedon one or more additional circuit layers. An example of this type of VSIyield enhancement is its application on high performance microprocessorwherein more than half of the IC is cache memory. Nine or morehorizontal interconnection layers are used in present state of the artmicroprocessors, however, this interconnect density is need only by themicroprocessor or logic portion of circuitry and not the on chip memory.The separation of the logic portion to a separate circuit layer resultsin limiting the lower yield process to only the logic circuit layer orlayers, and allowing the memory portion of the planar microprocessor ICbe fabricated with fewer horizontal interconnection layers. The memoryportion of the planar microprocessor circuit fabricated as separatecircuit layers will then have a higher yield, therefore, resulting in anet higher yield for an equivalent VSI microprocessor component.

VSI Process Method and Power Reduction

In many ICs the most significant source of power dissipation is from I/Odriver circuitry required for off die or off chip interconnections. TheVSI invention enables the reduction of circuit power dissipation throughvertical integration of two circuit layers and by eliminating the needto have conventional I/O driver circuitry to transmit signals betweencircuit layers. VSI integration reduces the total number of off chipI/Os that would be required if each VSI circuit layer were instead aconventional planar circuit using off chip I/O driver circuitry.

The VSI invention enables power management of various circuit layers andportions of circuit layers of a VSI die through vertical integration oftwo or more circuit layers by physically placing power control circuitryon one or more circuit layers other than the circuit layers of whichpower dissipation is to be controlled. The power control circuitrycontrols power dissipation from circuit layers or portions of circuitlayers by switching on or off the voltage supply and or clock signalscarried over vertical interconnections from the power control circuitrybased on system or application required use of the circuitry on thecontrolled circuit layers or portions thereof. The separation of thepower control circuitry to a separate circuit layer enables the powercircuitry to be fabricated from an IC process that is most appropriatefor this purpose and vertical routing of power and clockinterconnections simpler and shorter than in a planar implementation.

The VSI invention enables transistor leakage reduction through backsidefabrication processing of transistor body contacts to achieve a forwardbody bias in order to increase the transistor threshold voltage [V_(t)]or fabrication of a backside gate or dual gate. The backside processingpreferred embodiment uses a buried dielectric layer such as the oxideburied layer of a SOI [Silicon on Insulator] wafer substrate. In thepreferred embodiment the buried dielectric can be used as an etch stopfor precise thinning of the closely coupled substrate last bonded to theVSI substrate stack. Such controlled thinning allows contacts to be madeto the backside of a transistor without affecting the thickness of thetransistor body which can be less than 15 nm.

The backside processing enables the placement of contacts where biasingwith larger than the power rail can be applied. This allows the offleakage from source to drain regions of the transistor to be reduced oreliminated depending on the applied voltage. Fabrication of additionalcircuit element structures such as the fabrication of diode junctions byepitaxy means or the fabrication of a floating backside [dual] gate,which can be used to apply a non-volatile or permanent bias to thetransistor gate channel, is also enabled.

VSI Process Method and Test & Packaging Cost Reduction

The cost of testing and packaging of high I/O count planar ICs is oftenfar more than the manufacturing cost of IC die of the completed circuit.The VSI invention enables through vertical integration the reduction orelimination of testing and packaging costs by the incorporation of ATE[Automatic Test Equipment] functions as a circuit layer and thepackaging of two or more circuit layers eliminating the use ofconventional planar IC interconnecting means. Conventional ICinterconnection means of planar ICs are IC packages, package carriers orsockets for IC packages, multi-layer PCBs [Printed Circuit Boards] andPCB edge connectors.

Planar ICs are tested with the use of ATE systems which occurs more thanonce during the manufacturing process of a planar IC. The VSI inventionenables the incorporation of ATE functions as a separate circuit layerwhich places a fixed limit on ATE processing costs no matter how oftensuch tests may be performed for all the layers of a given VSI componentand with the fixing of ATE cost at no greater than the cost of one ofthe VSI component circuit layers plus the pro rata cost per IC of testprogramming. For example, if a VSI component has five circuit layers andone ATE circuit layer, the cost of test processing is reducedapproximately by a factor of five while enabling the performance oftesting with additional frequency at no additional testing costs. It iswell known that for certain ICs such as high performancemicroprocessors, longer test times are required to verify the properfunctioning of the IC. Further, such internal test capability enablesthe testing of the VSI component during its useful life.

Planar IC packaging with I/O count in excess of 500 can cost severaltimes the cost of the IC die they enclose. In order to interconnect anumber of such packaged planar ICs additional interconnection means suchas a PCB and package sockets are additional costs. The VSI inventionenables the reduction of the number of packages used to one or none.This is accomplished by the VSI invention, since any number of VSIcircuit layers need only require at most one package enclosure. Further,since VSI processing results in the enclosure of all circuit layersurfaces, which can be hermetic, no additional package enclosure may beneeded. For example, if a packaged VSI component has five circuitlayers, the packaging cost of the five circuit layers is reducedapproximately by a factor of five. This cost can be further reduced tonear zero, if the inherent self packaging capability of the VSIcomponent is used.

VSI Process Method for Circuit Design and Validation

The VSI invention reduces the complexity of circuit design andvalidation by enabling an arbitrary division of a planar IC into anumber of stacked circuit layers. This has the immediate benefits ofsimplifying functional and physical design, and validation. ICfunctional and physical design are simplified when a smaller physicalarea or size of a circuit layer is used; the partitioning of a largeplanar IC into several circuit layers allows changes to the functionalor physical placement of circuitry on one layer to affect only thecircuit layer on which the change is being made. By example, a change ina microprocessor circuit does not result in a physical change toassociated planar ICs that it may be connected to on a PCB. ICvalidation is simplified by fixing the timing analysis of a circuitlayer, and the signal timing between circuit sections on various circuitlayers through shorter vertical interconnection paths; powerdistribution is also simplified in the same manner. The VSI inventionallows the partitioning or division of a large planar IC enabling theinterconnect density of the various partitions to be maintained, therouting distance between circuit divisions to be shortened, and thetreatment of each circuit partition or circuit layer in a “black box”fashion, wherein once a circuit layer partition is completed it can betreated as a fixed entity that is not affected by subsequent circuitdesign changes on other layers. Further, a circuit partition that isphysically used multiple times in a planar circuit will vary in designfor each one of it uses, whereas as a VSI circuit layer partition hasonly one design. Present circuit design and validation software toolsfor planar circuits process the complete planar IC as a single entityresulting in longer processing times and software complexity. The VSIinvention enables circuit design and validation to be performed on acircuit layer basis wherein circuit design changes can be considered tohave affects limited to the circuit layer on which they occur.

The VSI invention enables a circuit design framework or platform whereincircuit layers of widely varying design and function, process andtechnology used previously on fabricated circuit designs can be reusedin an as is manner as circuit layers for a new IC application. Circuitlayers can be fabricated and held as inventory for subsequent insertioninto a VSI component application, and therefore, avoiding the need tointegrate the circuitry of this circuit layer into each and every newcircuit design such as in the design of planar IC. This circuit designaspect of the VSI invention is not available in present circuit designprocesses. IP [Intellectual Property] in the form of hard circuit designmust still be integrated and fabricated a new for each planar circuitapplication circuit use; the reference to reuse of such IP circuitry isin regards to it physical or logical design and not the reuse of the IPin a second application with the same fabricated circuitry from a firstapplication. This type of VSI design platform simplifies circuit designsby eliminating the design validation complexity of integratingpreviously designed circuitry or IP for each application circuit andreduces the circuitry to be designed to that uniquely required toimplement the desired application. For example, the advantages of theVSI design platform can be seen in applications regardingmicro-controllers where microprocessor and memory circuitry arefrequently unchanged for each application design and only peripheralcircuitry is unique to the application design; a VSI design platformallows the micro-controller and memory circuitry to exist as aninventory of previously fabricated IP layers that does not require adesign and validation effort for integration with the applicationspecific peripheral circuitry. Another example of IP of a VSI designplatform is tester circuitry. Tester circuit layers for broad classes ofapplications such as microprocessors, memory or analog can be insertedinto a VSI component and programmed for the unique testing requirementsof specific circuit layers of the VSI component application. The testingis accomplished through one or more tester specific fine grain verticalbusing interconnections common to some number of circuit layers and orcircuit layer vertical busing interconnections specific for use by suchtester circuitry. A further example of the VSI design platform is thedesign of a VSI component using a large number of functional circuitunits such as DSPs, FPUs, ALUs, MACs, Serdes, various SRAM, DRAM, MRAMmemory groups, ECC, etc. as circuit layers and not requiring the design,validation, placement or orientation of the functional blocks withrespect to each other as would be required in a planar IC design, whileinterconnection of these blocks would be through a placement conventionfor high density fine grain vertical interconnections or busing.

The VSI invention design platform further enables the means for theincorporation of redundant or spare circuitry in much the same manner asin the above examples. Yield of an IC is presently a result offabrication process and its ability to achieve specific defectdensities. The use of design to affect the yield of an IC only haslimited specialized use such as in DRAM ICs. A VSI design platformallows selective yield improvement or enhancement per circuit layer. Ifthe yield of a specific circuit layer of a VSI component is for example25%, if a redundant or spare of that circuit layer is added to the VSIcomponent layers, then the effective yield for that circuit layer [theprimary circuit layer or the spare] is enhanced to 44%, and if a secondspare is added the effective yield for that circuit layer is enhanced to58% or 1−[1−0.25]³. The benefit of the VSI design platform method foryield enhancement is the low design effort, and simplicity andselectivity for increasing the effective yield of any given circuitlayer of a VSI component. This circuit layer specific design approach toVSI component yield enhancement is preferably implemented through theuse of signal line bypass transistors and or power bypass to isolatedefective or spare circuit layers within the VSI component.

VSI Process Method and Self Packaging and Hermetic Sealing

The VSI invention enables self packaging and hermetic sealing of thecircuit die. This is accomplished by the thermal diffusion bonding usingthin film depositions of inorganic materials such as aluminum, copper orlow temperature glasses to form the bond between circuit layers. Sinceall IC surfaces of a VSI die can be made to be interior to the circuitlayer stack. The I/O pads used to make external connections to the VSIcircuit are formed on the backside of the last bonded circuit layer.This is accomplished by making vertical interconnections through thesemiconductor substrate of the last circuit layer where the substrate ofthis circuit layer may be thinned to a thickness of between 15 and 50 μmto provide a thicker separation between the circuitry of the lastcircuit layer and the bond pads formed on its backside. The verticalinterconnections to the bond pads and the bond pads are formed withconventional process means. No additional packaging enclosure is thenneeded to protect exposed IC surfaces of the VSI circuit resulting in aself packaged condition upon the completion of the fabrication of theVSI die, because none of the VSI circuitry layer surfaces have externalexpose, as shown in FIG. 3, FIG. 4 & FIG. 5 and FIG. 1 of inventor'sU.S. Pat. No. 5,915,167.

The process of bonding the circuit layers of the VSI circuit causes ahermetic seal of the surfaces of the circuit and wherein access to thesesurfaces is only from their exposed edges. The VSI invention achieves ahermetic seal depending on the type of bonding process used. Thermaldiffusion bonding process using inorganic materials achieves a hermeticseal, whereas a bond process using organic materials may not. Since allIC surfaces are interior to the VSI circuit then all of the IC surfacesare sealed and no additional hermetic packaging enclosure is required tocreate a hermetically sealed environment for the VSI circuit which isalways required for planar ICs.

VSI Process Method and I/O Pad ESD Isolation and Distribution

The VSI invention enables substrate isolation and distribution of I/Opads onto a separate circuit layer or the backside of a circuit layer.The placement of I/O pads over or in close proximity to active circuitryin planar ICs creates the opportunity for damage to the underlyingcircuitry from Electro Static Discharge [ESD]. ESD circuit structuresaround I/O pads are designed to couple the ESD to the substrate. Theplacement of I/O pads in a distribution pattern convenient to apackaging method is often incompatible with the placement and routing ofthe circuitry of a planar IC, therefore, I/O pads of planar ICs aregenerally located at the edge of the die to allow for fabrication of ESDstructures, this often results in what is termed a pad limited die sizewhere the size of the die is increased to accommodate the number ofperipheral I/O pads and beyond that needed by the area of circuitry onthe die.

ESD isolation of the I/O pad in a VSI die is accomplished withoutconcern of circuitry placement or resulting in I/O pad limited die sizebecause the I/O pads are formed on a separate circuit layer or on thebackside of a circuit substrate. Therefore, the fabrication of ESDprotection circuit structures and the distribution or placement of I/Opads, does not impact the placement and routing of VSI circuit layercircuitry. The benefit of this aspect of the VSI invention is smallerdie size resulting from the removal of the area normally allocated forI/O pads from the circuit layout, and the elimination for nearly allcircuit designs with the possibility of a pad limited die sizecondition.

VSI Process Method and Dielectric of Low K Value Constants

The horizontal circuit interconnections are typically formed indielectric materials of silicon dioxide, however, the integrationprogression below 0.15 μm [150 nm] has raised the need for materialswith lower dielectric constants than the nominal value of 3.9 providedby silicon dioxide. The fabrication method of the VSI invention enablesthe use of a vacuum or a fluid dielectric such as dry nitrogen or dryair resulting in a dielectric constant near or equal to unity forhorizontal interconnections. This is enabled by a combination of the VSIfabrication process and the removal of the dielectric material or asacrificial material such as amorphous silicon or low temperatureglasses used in place of the dielectric material. FIG. 7A. shows incross-section free standing vertical and horizontal interconnections 74a in a cavity formed as part of a circuit layer. The VSI fabricationprocess forms a hermetic seal 76 b at the edges of the surfaces of theindividual ICs of a circuit layer and or of a wafer or substrate duringthe bonding process step. During circuit layer fabrication a dielectricmargin support 73 b is formed along the edge of each IC of the VSIcircuit layer, and in the area at the edge of a die when arrayed as partof a substrate which is referred to as the die scribe lane 79; theforming of a hermetic seal does not require additional processing steps,is compatible with the metal interconnect processing steps and isaccomplished through the design of the layout of the circuit layer.After the completion of the fabrication of horizontal interconnectionsand prior to wafer bonding the dielectric or sacrificial material isremoved by selective etching or a dissolving solution leaving a freestanding structure of horizontal interconnections; similar to some MEMSprocessing techniques used to make free standing metal structures. Thismethod of forming a low-k dielectric separation between horizontal andportions of vertical interconnections of a circuit layer is hereinreferred to as VSI low-k dielectric. The free standing horizontalantennas for Rf transmission and reception can also be formed in thismanner.

The horizontal interconnection structure remains without collapsing dueto the low mass of the interconnection wires [measured in μm grams orless] and the typical use of low tensile stress deposition methods offorming the metal interconnects which are made primarily from aluminumor copper. The free standing interconnect structure is supported at theedge of the die by the dielectric margin of the IC 73 b and where also ahermetic seal is formed, and as may be required by the design of thehorizontal interconnection layers or IC die size, support columns orposts formed with the interconnection structure as part of theinterconnection fabrication process or subsequent to the formation ofthe interconnection structure but before the removal of the dielectricor sacrificial material. The vertical interconnections of the VSIfabrication process are formed as columns as required over the surfaceof the circuit layer. Once the circuit layer is bonded on to the VSIcircuit substrate stack the free standing interconnect structure isprotected from subsequent damage of continued VSI circuit layerprocessing and when the VSI component is cut from the substrate stack,it can be handled in the same manner as any other VSI component.

A further advantage of the removal of the dielectric material or the VSIlow-k dielectric method when such metal interconnection materials suchas Cu [copper] are used, is the reduction or elimination of therequirement for a barrier layer about the exterior of theinterconnection. It is well known that a barrier layer such as TiN isrequired to enclose copper interconnections in order to prevent thediffusion of copper atoms in to the dielectric. It is not possible forcopper to diffuse through a VSI low-k dielectric material. Theelimination of the requirement to form a barrier layer enclosing theinterconnections increases the conductivity of the interconnections andreduces the cost of fabrication. The interconnection conductivity isincreased as a result of replacement of the barrier layer withadditional interconnect material; all present barrier layer materialshave lower conductivities than the preferred interconnection material ofCu now used and for circuit geometries of less than 120 nm the barrierlayer thickness surrounding the interconnection can occupy more than 10%of the volume of the physical interconnection, and therefore, thecombination of the barrier and interconnection material results in a netlower conductivity of the interconnection than if the barrier layer wasnot present. A cost reduction results from the elimination of the costin forming the barrier layer.

VSI Process Method for Multiple Path Access to Memory for ErrorDetection and Correction

The VSI invention enables the use of conventional busing structures andmemory organization to achieve various error correction methods. Whentwo or more fine grain vertical bus paths to memory are used where thedata or control information is transmitted on a separate bus from theerror encoding information, the memory array structure does not need tobe uniquely designed or structured to accommodate the amount errorencoding information as is the case with current memory designs. Twoexamples of this is parity encoding which adds one bit of errordetection information for every eight [8] bits, and ECC which can addtwo or three additional error detection and correction information bitsfor every eight bits of information.

This aspect of the VSI invention allows a number of vertical bus pathsto memory to be implemented without the need to be designed to support aspecific error detection or correction method, but to be designedwithout accommodation to any specific error detection or correctionmethods. The error information would be provided by one or more of theavailable bus paths to memory and programmable processing logic woulddecide where and when the method to apply if any to determine ifinformation from memory is in error. The benefit of this partitioning ofinformation and error code data of the information, simplifies thedesign of memory structure, does not require the error detectioncorrection methods to be a fixed capability designed into the memorystructure and enables a choice of when to apply a memory error detectioncorrection method for some segment of stored information and which typeof method to apply.

VSI MEMS Integration Methods

MEMS [Micro-Electro-Mechanical Systems] can be integrated as one or morelayers of a VSI component using the VSI fabrication technology. A MEMSlayer can be integrated as a separate layer or as an internal layer of aVSI component or group of VSI circuit layers or incomplete VSIcomponent.

The VSI stacking fabrication processing sequences are sufficient toincorporate the inclusion of MEMS layers with minor or no modificationallowing direct interconnection to the various circuit or device layersof a VSI component through fine grain vertical interconnections. Thereare two preferred VSI component MEMS fabrication sequence embodiments.These are:

[1] MEMS device substrate as the first layer of a VSI component: Thissequence is:

-   -   [1.1] Bond, preferably by thermal diffusion bonding methods,        circuit layer top side down [face side down], this also seals        and provides a protective cover of the open surface of the MEMS        device.    -   [1.2] Thin as necessary circuit layer substrate or wafer and        complete fabrication of circuitry and fine grain vertical        interconnections on circuit layer backside.    -   [1.3] Continue the VSI fabrication stacking sequence. This        sequence is the same as that used in completing a VSI component        stack or for inclusion of additional MEMS layers as outlined        below in the second VSI MEMS fabrication sequence.

[2] MEMS as an internal VSI component layer: This sequence is:

-   -   [2.1] Bond MEMS wafer layer onto an incomplete VSI component        substrate or wafer stack. This typically would be done with the        MEMS surface side of the wafer as the bonding surface; this        seals the MEMS devices and allows subsequent processing of the        backside of the MEMS wafer.    -   [2.2] Thin as necessary MEMS substrate or wafer and fabricate        circuitry and fine grain vertical interconnections as needed.    -   [2.3] Continue the VSI fabrication stacking sequence. The MEMS        layer may be the last layer of the VSI component or any        arbitrary number of additional circuit layers and or MEMS layers        may follow.

It should be further noted regarding VSI MEMS fabrication:

[1] Some MEMS substrates cannot be thinned from the backside to allowfabrication of VSI fine grain vertical interconnections. In these casessuch MEMS devices would be restricted to being the first or bottom VSIlayer so that fine grain vertical interconnections can be originatedfrom the MEMS device surface of the MEMS substrate.

[2] A MEMS device can be fabricated [in situ] as a layer of a VSIcomponent if its processing sequence steps [typically thermal steprequirements] do not damage the existing VSI layers. This processingsequence can be implemented by first processing the backside of thesubstrate onto which the MEMS device is to be subsequently fabricated,wherein circuitry and fine grain vertical interconnections are formed toenable interconnection to and bonding onto a VSI component stack, aftersubstrate bonding, the substrate surface to be used for MEMS devicefabrication is available for processing. The processing sequence of theMEMS device will include processing steps to form verticalinterconnections from the backside of the MEMS substrate for use by theMEMS device and connection to any additional VSI device layers.

[3] A MEMS device may require placement as the bottom layer of a VSIcomponent but with its device surface [top surface] allowed to face outfrom the VSI component [into the environment] as may be required by anoptical array. This is facilitated first by bonding the MEMS substrateto a temporary substrate with a release layer allowing its removal or apermanent transparent substrate such as glass, quartz or an applicationcompatible substrate. In this manner, the backside of the MEMS substratecan be thinned as needed to allow fabrication of fine grain verticalinterconnections and subsequent VSI processing.

The VSI process enables the integration of MEMS devices and a majorityof semiconductor electronic or optical circuit types. This is possiblebecause there is no requirement to merge the fabrication processes ofthe MEMS device and circuitry as would be the case in a planarfabrication that combined MEMS and circuit fabrication. The VSI processseparates or segregates the typically incompatible fabrication processesto layers of a VSI component, and thereby avoids this particularlydifficult problem. Presently MEMS devices cannot be integrated withstate of the art semiconductor circuitry such as CMOS in a single die.The VSI process enables the integration of MEMS devices withsemiconductor electronic or optical circuitry into a common or singledie.

There are numerous benefits of VSI component MEMS integration, some ofthese benefits are a generic and simple method for integration ofelectronic and or optical circuits with a MEMS device, VSI processhermetic seal and self packaging, short wiring interconnections betweencircuit layers and MEMS device layers of typically less than 0.5 mm to 1mm, higher analog circuit fidelity and lower noise from shortinterconnect length, smaller net IC and MEMS footprint size, greaterinterconnect density and the anticipation of low cost.

VSI Optical Circuit Layer Integration Methods

Optical circuits fabricated with semiconductor processing means can beintegrated into a VSI component with the same VSI fabrication processingsteps as those used for electronic circuit layers. In the preferredembodiment, optical circuits can be bonded onto a VSI component stackwith dielectric or metal thermal diffusion bonding and then thinned asneeded to allow fabrication of optical connections on the backside ofthe optical circuit layer or vertical optical interconnections to othercircuit layers.

The switching of optical input signal to optical output signals is nowaccomplished by converting incoming optical signals from a given opticalinput to electronic signal to make the determination onto which outgoingoptical signal the incoming information from the optical signal shouldbe forwarded or output. This presently involves the use of a number ofdiscrete optical and electronic circuits assembled on a PCB [PrintedCircuit Board] or MCM [Multi-Chip Module]. The VSI invention enables theintegration of optical and electronic circuits into a singleOptical-Electronic [OE] IC or die or Optical-Electronic-Optical [OEO] ICor die.

Such OE or OEO ICs reduce the cost of optical switching applicationsthrough reductions in packaging and IC package to IC packageinterconnection costs. Such OE or OEO ICs improve optical switchingperformance by coupling the electronic circuitry on layers withindistances of microns to either optical input or output means; thisreduces the delay time of electronic signals both from between theoptical inputs and outputs and electronic circuitry, but also among thenumerous electronic circuit means that comprise the electronicprocessing portion of the VSI OE or OEO IC, such as programmableprocessors, programmable logic [PLDs] and memory.

The VSI OE or OEO IC structure enables the integration of active andpassive optical signal processing components such as modulators,filters, optical sensors and laser diodes, or WDMs as separate VSIlayers in the OE IC. Planar optical circuits are increasingly beingfabricated on silicon or similarly sized substrates and with processesthat are compatible with semiconductor electronic circuit fabrication.The VSI process directly integrates such optical circuit substrates orwafers into a VSI substrate stack or component as long as, at a minimum,the edge surrounding the optical circuit die is sufficient planar foruse by one of the VSI substrate or wafer bonding processes.

FIG. 10 shows the integration of an optical circuit layer into a VSIcomponent IC stack 104 which is mounted on a support substrate 103.Optical signals are received by way of an optical fiber connection 101a, 101 b passing through and attaching to support substrate 103 andsensed by photodiodes 102 on one or more circuit layers of the VSIcomponent 104 where these optical signals are converted into electronicsignals. The optical signals may also be routed between optical circuitlayers of the VSI component 104, prior to their conversion to electronicsignals, by means of optical planar wave guides and reflective cornermirrors or facets fabricated on an optical and or electronic circuitlayer or by means of layer to layer coupling by placing opticalwaveguides [using voids or dielectric materials with appropriatelychosen indices of reflection] into physical proximity as a result of thesubstrate or wafer bonding process. Electronic signals are converted tooptical signals from within the VSI component by laser diodes on one ormore circuit layers and routed from the VSI component via planarwaveguides on one or more circuit layers terminating into one or moreoutput optical fiber connections.

VSI ATE Method for Internal Self Test

Another embodiment of the VSI invention is the use of self testcircuitry as a layer that can be programmed to test one or more logicand or memory type circuit layers of a VSI component. These self test orATE [Automatic Test Equipment] circuit layer or layers may have many ofthe design and operating characteristics found in present ATE systems,however, the VSI self test or ATE circuit layers offer fundamentaldifferences in operation and capabilities versus externally applied ATEsystems. The VSI self test or ATE circuit layers may rely on or make useof the internal memory layers of the VSI component to store some or allof its test vectors, and can perform its testing procedures of the VSIcircuit layers of which it is a part on demand, such as duringmanufacturing burn-in processing or at anytime during the useful life ofthe VSI IC or VSI component. The use of the ATE term with respect to aVSI test circuit layer or layers is intended to make clear that such VSIcircuit layers are generic programmable VSI circuit layers with as muchor more of the test function capability as an ATE system and intendedfor integration into VSI components for use in testing a broad range ofVSI component applications. The test function logic of an ATE system canbe integrated as one or two planar ICs, however, at least therequirements for very high throughput resulting in large complex testvector memories and very sophisticated transmission interconnectionpaths in order to propagate test signals to the DUT [Device Under Test]with matched timing from the ATE to the DUT have prevented the ATEsystems from benefiting from advances in IC integration to the samedegree as the ICs the ATE systems are intended to test. Theselimitations or disadvantages do not exist for the VSI ATE logic circuitlayers for the following reasons: the use of a smaller internal VSIcomponent memory is sufficient because there is not a high throughputrequirement for processing a number of ICs per hour, as with ATE systems[due to the large capital cost of the ATE systems], the internal VSIcomponent memory can be loaded repeatedly with additional test vectordata until the desired testing is completed, and therefore, largecomplex test memories are not need; the VSI ATE interconnections to theother VSI circuit layers are through fine grain verticalinterconnections which are too short to create signal propagation timingdifferences, and therefore, the complex signal transmission interconnectand circuitry are not needed; and further, as a consequence that the VSIATE circuit layers are closely coupled to the circuit layers of the VSIcomponent, the power requirement of the VSI ATE is nominally 1,000 to10,000 times less than a ATE system and the number of ATE test contacts,generally referred to in the ATE art as “pins” can be increased bygreater use of VSI vertical interconnections with only marginalincreases in power dissipation, and most distinguishing versus ATEsystems, little or no increase in VSI ATE fabrication cost.

The integration of an ATE circuit layer into a VSI component requiresthat there is sufficient internal memory to support the operation of theATE processing logic, and the added cost of the ATE layer for mostapplications be less than the combined testing costs of the individualdevice layers that may be included in the circuit design of the VSIcomponent. The inclusion of the ATE circuitry becomes a reasonableconsideration in the use of the VSI invention given the rising cost oftesting for such complex logic circuitry as microprocessors or networkprocessors where their test costs presently exceeds their fabricationcosts, and wherein the duration of present external ATE testing does notprovide exhaustive fault coverage of the circuit. The VSI ATE method forIC testing allows a fixed cost of ATE logic usage for whatever durationof testing, this is not the case with current ATE systems because suchsystems have very high capital costs and this results in a trade-off oftest usage costs versus adequate IC test coverage. The cost per VSIcomponent of the VSI ATE method can nominally be estimated as a fixedcost of approximately the cost of one circuit layer of a VSI component,and independent of the duration of testing conducted on the VSIcomponent.

The operation of the ATE circuitry testing program can be loaded undercontrol of external logic or by internal logic of the VSI componentunder test. The test vectors used by the ATE are loaded into the memoryof the IC or VSI component and testing is conducted as needed tocomplete the desire level of fault coverage for a given device layer orgroup of device layers. This process is then repeated as needed for thetesting of all device layers of the IC including the testing of opticaland MEMS device layers. One of the significant differences of the VSIATE test method versus present external ATE system testing methods isthat it enables VSI component or IC testing to be conducted for extendedperiods of time and at the maximum performance rate of the VSI componentin either burn-in facilities or low cost PCB test fixtures, and afterassembly in an end use application.

Other manufacturing benefits of internal ATE circuitry in addition tolower circuit test cost are at-speed testing of the IC, testingsufficiency for greater IC fault coverage, no additional IC testhandling or requirements for IC bare die or packaged tester interfacefixtures. The fabrication process used to make the ATE circuitry canmatch the state-of-the-art fabrication process used for any of the otherelectronic circuit layers of the VSI component. The electronics used incurrent state of the art ATE systems are generally two to three ICgenerations behind IC state of the art fabrication processes, andtherefore, are often insufficient to provide the testing performancecapability that IC manufacturers seek, and greater automation of the ICmanufacturing process.

VSI Yield Enhancement Methods

The VSI integration process invention incorporates several circuit yieldenhancement methods. These methods vary in application but aredistinctly enabled through the VSI integration process. The term yieldused herein is the percentage of accepted [passed] VSI components orcircuit die of the total number of available die per VSI wafer orsubstrate stack.

The VSI yield enhancement methods of the invention are presented belowin an order intended to show that there is a progression of capabilityof the VSI yield enhancement methods.

VSI Yield Enhancement Method 1, Die Size Reduction

The VSI invention enhances die yield by allowing a large planar circuitdie to be partitioned into some number of circuit layers each with thesame die size but with a reduced die size versus the original planarcircuit. The statistical yield of a VSI die is higher versus theequivalent planar die. This is the due to the existence of thenon-linear relationship of yield versus die size. The VSI integrationprocess enables IC fabrication processing to uniquely utilize thisnon-linear relationship.

As an example, a die of 400 mm² in a current CMOS logic or memoryprocess may have a yield of less than 20% whereas a die of 25 mm² in thesame process may have a yield of 96%. The yield of an equivalent VSIcomponent or die made of 16 25 mm² circuit layers is (0.96)¹⁶=0.52 or52%. This yield enhancement is a statistical result and in alllikelihood is a consequence of IC fabrication processes, but is a yieldenhancement result uniquely attributable to the VSI integration process.

VSI Yield Enhancement Method 2, Wafer Tiling Efficiency

The VSI invention enhances die yield per wafer or substrate by allowingthe size of a planar die to be reduced by partitioning portions of aplanar circuit design onto separate circuit layers to achieve a higherwafer tiling efficiency or a greater number of physical die per wafer orsubstrate surface area. This increases the total number of dicefabricated per wafer, and therefore, for some percentage yield, agreater number of total good or usable dice.

The VSI dice per wafer yield enhancement quantitatively varies in arange approaching 25% greater die per wafer or substrate and can beshown by the example of a 520 mm² planar die and an equivalent VSIcomponent or die with a size 66 mm² and 8 circuit layers. The 520 mm²planar die will have a wafer tiling efficiency of approximately 74% or44 die per 200 mm diameter wafer. The equivalent VSI component or diewill have a wafer tiling efficiency of approximately 85% or 400 die perwafer. This results in a net increase of 48 additional die or 14%, or anincrease in die per wafer [VSI stack] yield of approximately 14%. If theVSI die size is decreased to 33 mm² there is a net increase of 149 dieor an increase in die per wafer [VSI stack] yield of approximately 22%.

The increased number of circuit die per wafer results in increased dieper VSI wafer or substrate yield. The reduced die size used in thismethod of VSI yield enhancement is further improved, and unavoidablybenefits, from VSI yield enhancement method 1.

VSI Yield Enhancement Method 3, Process Separation

The VSI invention enhances die yield by allowing the separation orsegregation of high complexity processes or technologies which havelower yield to be restricted to a smaller physical size when integratedwith high yield processes or technologies. The VSI invention allows thesize or physical dimensions of a VSI component or die [not the totalarea of all circuit layers] to be determined by the maximum amount ofcircuitry desired per circuit layer rather than the total amount ofcircuitry to be fabricated onto the die as is the case with planar ICs.The net yield of a VSI component or die per wafer or substrate,therefore, is the combined yield of the separate or segregated circuitlayers made with lower complexity processes or a combination of higherand lower complexity processes, as compared to the yield of equivalentplanar circuitry requiring the merger of two or more distinct circuitfabrication processes resulting in a more complex process with higherdefect density and lower yield. The VSI component or die yield will bealways greater because the complexity or defect density per VSI circuitlayer is lower resulting in a higher net yield of VSI components. Thisyield effect of the VSI process can be stated as resulting from asemiconductor industry established fact that the defect density ofmerged IC fabrication processes are always greater than the defectdensities of those IC fabrication processes if utilized separately.

An example of this specific VSI yield enhancement method is theapplication of the VSI invention to high performance planarmicroprocessor, communication or graphic processors which incorporateboth logic and large amounts of one or more types of memory. Such planarprocessor circuits are generally designed with a significant percentageof their circuit surface area allocated to memory circuitry. The logiccircuitry typically uses a transistor fabrication process that is morecomplex or significantly different from those used for fabrication ofthe memory circuitry. The logic circuitry presently may require nine [9]or more horizontal interconnect metallization layers whereas the memorycircuitry typically requires less than four [4], and in the case whereembedded DRAM memory is used, the logic and memory cells are formed withtwo different processes. The fabrication yield of the logic circuitry isusually less than that of the memory circuitry due to its greaterfabrication complexity, therefore, the combination of two or moredistinct fabrication processes increases the total number of processsteps required to produce the a planar IC resulting in a lower netcircuit yield than if the logic and memory circuitry where fabricated asseparate planar circuits. The VSI invention enables the logic and memorycircuitry to be fabricated separately and integrated as separate closelycoupled circuit layers of the VSI component or die. Therefore, yield ofthe VSI die is higher than a planar die equivalent because the net yieldof the individual and separate logic and memory circuit layers of theVSI die are higher. A further aspect of this yield enhancement method isthat it has a lower cost of manufacturing, and therefore, lower net diecosts result from both a higher yield and cost savings frommanufacturing wafers or substrates with fewer process steps. Thefollowing is an example of this VSI yield enhancement method. Thepercentage logic circuitry of planar die surface area in current highperformance microprocessors such as 32-bit and 64-bit circuits with adie size of 200 mm² is less than 25% with the balance generally givenover to memory circuitry. An equivalent VSI component or die of theplanar circuit would consist of the logic layer and three memory layers.The estimated yield of the VSI logic layer is 85% and 94% for each VSImemory circuit layer, the estimated yield of this VSI component would beapproximately 70% versus an estimated yield for the equivalent planarcircuit of 40%.

Another example this specific VSI yield enhancement method is the use ofnon-silicon fabrication technologies such as GaAs, InP or InSb for logicand CMOS memory. If GaAs is used as the non-silicon semiconductortechnology, it is well known that the yield of GaAs is significantlyless per unit area than that of digital logic CMOS or for such a CMOSmemory as SRAM. Presently there are no commercially produced examples ofplanar ICs with merged GaAs and CMOS technologies, however, it isreasonable to estimate that the yields of such planar circuits would besignificantly less than the yields of their separate GaAs and CMOScircuit portions if fabricated as separate planar circuits. Thecapability to integrate different semiconductor technologies into asingle die would enable the integration GaAs optical transceiverscircuitry and digital CMOS, simultaneously improved performance overpresent discrete IC implementations and at lower cost. The fabricationof different semiconductor based circuits as circuit layers under theVSI process and in combination with VSI backside interconnect fine grainvertical interconnect fabrication means allows wiring connections to bemade on the basis of individual circuit elements or devices between thetwo distinct semiconductor technologies by virtue of the placement ofsuch devices in close proximity either directly above or below eachother, and therein, achieve a circuit integration equivalent to planarintegration. This method of VSI yield enhancement by circuit layercomplexity reduction or separation can be further improved by use of VSIyield enhancement methods 1 and 2.

VSI Yield Enhancement Method 4, Vertical Redundancy

The VSI invention enables yield to be primarily determined by a specificportion of circuitry instead of circuit yield being directlyproportional to total surface area of all VSI circuit layers. In thismethod of the VSI invention, the portion of circuitry affected by adefect is small preferably less than 0.5 mm² in size. The size isimportant because when a defect is found the affected area of circuitryor the portion of circuitry that can be isolated and replaced by anidentical spare is preferably small. This is VSI fine grain redundancyand allows a circuit to be repaired through the availability of 100%circuit logic redundancy which is structured as shown in FIG. 11A. InFIG. 11A functional unit F11 can be replaced by F21 or F31 which arepositioned in close vertical proximity which allows verticalinterconnections 1101 a to all three units to be of similar length andrequire a minimum of horizontal interconnection wiring; it should beclear that a planar placement of these same functional units wouldrequire wiring lengths that would vary significantly from each unit.Similar wiring length efficiencies are represented by verticalinterconnections 1102 a and 1103 a.

FIG. 11B and FIG. 11C contrast the wiring length efficiencies of VSIvertical fine grain interconnections with planar interconnections. FIG.11B shows in cross section a planar IC 1104 b with logic unit 1102 b andspare logic unit 1101 b which are separated by wiring length dh 1105 b.Redundancy control unit 1103 b is used to enable the use of either logicunit 1101 b or 1102 b. FIG. 11C shows in cross section a three VSIcircuit layers 1104 c, 1105 c and 1106 c with logic units 1101 c, 1102 cand spare control logic unit 1103 c vertically aligned and positioned onone each of the three circuit layers. Logic units 1101 c and 1102 c havea vertical wiring length of dv 1107 c. The dh 1105 b wire length willvary widely because it is dependent upon the placement and size of logicunits 1101 b, 1102 b and any requirements on their placements relativeto other logic unit circuitry. It would not be unusual that dh havenominal wiring length values in a range of 500 μm to 2,000 μm. The dv1107 c wire lengths only dependent on the number of vertical layerseparations of the logic units 1101 c and 1102 c which in most caseswill be in a range of 10 μm to 20 μm. The wire lengths of dh arenominally 50 to 200 times greater than dv. The wire length variances ofdh are significant to the performance of an IC and will cause thecircuit timing to be a function of the longest wiring lengths betweenthe logic units, this may cause the timing performance of the circuit tobe inadequate. Secondly, the placement of spare circuitry will causeadditional wiring lengths between a number if not all of the other logicblocks of a planar IC and again resulting in lower or inadequate circuitperformance. It can be easily seen from this comparison that a 100% or200% VSI circuit redundancy will not affect circuit performance as aresult of wiring length delays, and that the use of the VSI method ofredundancy is not only transparent to performance but also to the layoutor placement of the IP or circuit blocks of a given circuit layer.

The unique difference of this method is that the majority of horizontalwiring layers are on one side of a circuit layer with one or morecircuit element or element group spares directly below each primarycircuit block that can be replaced if defective. This type of fine graincircuit redundancy nominally results in yields of greater than 99%. Thereason for this very high yield is that the portion of circuitry beingspared is small enough to have an effective yield of 99.99% and there isat least one [1] available spare to replace it should it be defectiveproviding an effective yield for the primary circuitry and its spare of1−[1−0.9999]²=99.999999%. This yield per configurable circuitry portionenables 90% yields for logic circuit layers of greater than1,000,000,000 transistors with the assumption that each sparing portionof circuitry has 10 transistors or more and some number of the firsthorizontal interconnection layers such as the layers generally referredto IC layout art as M1, M2 and or M3.

Selection of the primary or spare circuit portion is accomplished by arow and column orthogonal wiring matrix on the backside of the primarycircuit layer or on the spare circuit layer[s] which can select andconfigure the use of spare circuitry on the spare circuit layer astemporary or permanent. This type of sparing interconnection, allows forthe repair of circuitry in a VSI component throughout its useful life.This method of yield enhancement has little if any impact onconventional planar circuit design methods because the spare circuitryis vertically below or above the primary circuitry with fine grainvertical interconnection providing the wiring for enabling the use ofthe spare circuitry, and therefore, the logical or physical design ofany circuit is unaffected. This method lends itself for automation bythe physical layout CAD tools used for present planar circuit designbecause this method does not cause changes to the planar circuitryplacement. The CAD tool would insert fine grain vertical interconnectionrouting to sparing circuitry as a vertical overlay of a circuit designwith interconnections for circuit sparing made from the backside of aprimary circuit layer.

Fine grain vertical interconnections and pass transistors orfuses/anti-fuses can be used to replace the primary circuitry with thespare circuitry in the event of a defect in the primary circuitry. Theefficiency or cost reduction of this VSI invention is provided throughits high yield and the ability of the VSI process to integrate identicalcircuit layers organized in circuit blocks to the horizontal wiringlayers of one circuit layer.

Vertical buses are themselves sources of IC defects from fabrication ofthe vertical bus interconnection or the logic used to interface to thebus vertical interconnections. The area used per circuit layer even forbuses with large numbers of wires such as 1024 or 4096 verticalinterconnection wires is relatively small. The area required for a busof 4096 vertical wires with a 2 μm wiring pitch and its drive logic isapproximately 0.03 mm². It is cost effective to make portions of a busreconfigurable with spare or redundant logic or wiring portions or tohave a fully redundant bus in close proximity to the primary bus.

VSI Yield Enhancement Method 5, Yield Factoring

The yield of memory, PLDs and multiprocessors VSI components or ICs canbe determined from the yield of one or two circuit layers, therefore, ayield of 90% or higher can be expected no matter how large the actualcircuit area. This method of VSI IC yield enhancement combines the useof circuitry sparing and the incorporation of test and reconfigurationlogic.

This VSI invention method for circuit yield improvement combines the useof the VSI fine grain vertical interconnect, the ability to isolatewhole circuit layers or arbitrary portions of circuit layers throughpass transistors, fuses, anti-fuses or other electronic device, andyield management control, test and reconfiguration logic. The VSI finegrain vertical interconnect requires little surface area forimplementation of large number interconnections on a circuit layer andtypically no additional horizontal interconnect layers are needed inorder to connect yield management control logic which resides preferablyon one of the layers of the VSI component or can be partially externalto the VSI component.

The VSI yield methods are uniquely enabled by the novel aspect of finegrain vertical interconnect that provides significantly greaterdensities of circuit interconnections than possible with horizontalinterconnect and without additional process complexity. This VSI yieldenhancement method requires a greater level of interconnect than can beprovided by horizontal interconnect at present with 8 to 9 layers oreven the 14-16 layers anticipated in the future. This aspect of finegrain vertical interconnect is demonstrated when considering that finegrain vertical interconnections implemented with a 2 μm pitch enables aninterconnect density of 250,000 interconnections per 1 mm² or theequivalent of 125 horizontal interconnect layers of 0.25 μm pitch overan area 1 mm wide.

This VSI yield method achieves yield improvement by partitioning a VSIcomponent by circuit layer, Circuit Block of a circuit layer or acircuit element of a circuit layer that is vertically interconnected toone or more spare circuit equivalents. Such spares are enabled by yieldmanagement control logic. The yield management control logic typicallyon a separate circuit layer. The yield management control logic usesself test circuitry or internal VSI ATE [Automatic Test Equipment]circuitry to determine the presents of a defective circuit layer,Circuit Block or circuit element. If a defect is found by the internaltest circuitry, the yield management control circuitry usesreconfiguration circuitry to disable the defective circuit layer,Circuit Block or circuit element and enable spare circuitry replacement.

This VSI method of yield enhancement is efficient for the followingreasons:

-   -   1 Multiple circuit spares can be placed vertical association or        proximity to a primary circuit.    -   2 Vertical interconnection density is able to meet the        interconnection density required by circuit sparing.    -   3 Conventional circuit layout techniques can be used since        circuit spares are on separate circuit layers.    -   4 Internal yield management control circuitry, self test or VSI        ATE circuitry, and reconfiguration circuitry can be generic or        non-specific to the application circuitry it is embedded with in        the VSI component. This circuitry can exist on inventory or pre        existing VSI circuit wafers or substrates for immediate use and        do not require circuit design layout for integration into the        application circuitry.

This VSI yield method is not restricted to die size since yield isdependent on sections of circuitry of a circuit layer or Circuit Blocksthat have a surface area that is smaller than the circuit layer or die.However, the use of a die size of less than 200 mm² and preferably 50mm² or less, reduces the fabrication horizontal interconnectioncomplexity of a circuit layer, and therefore, the likelihood that acircuit defect will occur on a specific circuit layer and less so perCircuit Block. The reduced fabrication complexity results from fewactive Circuit Blocks types, and therefore, typically a reduced numberof horizontal interconnect layers. The die yield model for planarcircuits resulting from the established and traditional semiconductorfabrication process quality enhancement methods is directly related todie size. This VSI yield method uses the established planar fabricationyield method benefits for smaller die or Circuit Blocks in combinationwith fine grain vertical interconnect to achieve higher yields for VSIcircuits by raising the expected yield per layer than would be possibleif the separate VSI circuit layers were made as one planar circuit. TheVSI small die size yield enhancement method benefit is more clearly seenwhen considering semiconductor technologies or processes that whenmerged on a common substrate [versus implemented separately as VSIcircuit layers] are known to have lower yields such as in the case ofmerged GaAs and CMOS technologies or digital CMOS and DRAM memory cells.

The yield management enhancement circuitry isolates a whole VSI circuitlayer, portion or portions of a circuit layer from the operation of thetotal circuit. It also can enable the operation of a whole circuitlayer, portion or portions of a circuit layer for operation with thetotal circuit. There can be multiple yield management control logicunits which are specialized to work with various circuit types such asDRAM, Flash, PLD, analog circuit arrays, passive circuit arrays, MEMS,microprocessors, network custom processors, etc.

The VSI yield method is independent of die size. This is to say thatwith sufficient spare or replacement circuit portions, and or sufficientredundant circuit layers, the die size can approach the size of acomplete wafer for such applications as full wafer circuit test andburn-in [a MEMS application wherein micro-probe points are integrated onthe surface of a VSI wafer stack].

VSI Wireless Interconnection Array and Applications

Semiconductor fabrication methods are expected to reduce the cost ofplanar integration of 10 billion transistors per cm² to less than a fewdollars within the not too distant future. The availability of suchlarge quantities of low cost transistors provides the opportunity forimplementing information processing electronic subsystems or equipmentsolutions by using increasing amounts of parallel circuit functions.What has been and continues to be a clear limitation on the use of suchlarge numbers of transistors is the ability of current planar ICfabrication technology to provide sufficient interconnection density ofthese transistors. The interconnection requirements of an array [n by m]of transistors as the quantities [n] and [m] become very large increasein an exponential manner resulting in the use of greater numbers ofinterconnection metallization levels or methods that compromise or tradelower interconnect performance for fewer metallization levels. The costand technology limitations of greater numbers of interconnectionmetallization levels will result in lower utilization of future lowercost transistors, and therefore, the potential benefits to be gainedfrom these transistors are reduced or potentially eliminated.

Circuit layer stacking as shown by the VSI invention has a firstenabling benefit of increasing the number of interconnections orinterconnection density between any two IC layers while simultaneouslylowering the net cost of achieving greater interconnection densitythrough the use of various well established semiconductor fabricationmethods. The VSI invention provides greater interconnectionmetallization density through interconnect metallization scaling throughthe arbitrary addition of three dimensional [k by n by m] circuitrywhich is independent of the fabrication process used for making any oneof several possible circuit layers of the VSI IC. This thereby increasesthe planar [n by m] interconnection metallization limitations by [k]times. The VSI method for increasing interconnection density increasesthe utilization of future lower cost transistors, and therefore, thebenefits that can be gained from these lower cost transistors.

When an IC is packaged similar interconnection limitations return. Whena VSI IC or conventional planar IC is packaged and there is arequirement for forming large numbers of I/O connections betweenpackaged ICs, the IC designer is no longer able to take advantage ofsemiconductor fabrication cost reduction advantages. This is an obviousproblem currently seen where packages in excess of 600 I/O connectionscan cost far more than the ICs they contain, and reduce the potentialperformance while increasing the operating power requirements of theinterconnected collection of such ICs. Once again, for large numbers ofinterconnections between separated VSI ICs, similarly stacked ICs orplanar ICs, a solution for the problem of reducing the cost andperformance disadvantages of the high density physical I/Ointerconnections between ICs bare or package is needed.

Large computational or communication switching equipment or systems arepresently assembled using planar IC and PCB [Printed Circuit Board]technologies. These systems use numerous microprocessor ICs that operatein parallel and in conjunction with other ICs such as memory ICs toachieve an intended performance capacity. These systems are typicallyassembled from a number of PCBs wherein a PCB has mounted on it one ormore microprocessors or processors and associated support ICs such asapplication specific logic ICs, memory ICs and bus I/O orinterconnection ICs and may be generically referred to in industry asprocessor PCBs or processor modules. These processor modules are thentypically plugged into another PCB often called a backplane whichprovides one or more wired interconnection paths between all theprocessor modules; in addition, there may be cabling connections betweenthe processor modules to improve the data access and transfer ratebetween processor modules; such cabling may take the form of a bundle ofcopper transmission wires or one or more fiber optic transmission lines.A PCB backplane interconnection is often a shared or multiplexedinterconnection resource of the processor modules plugged into it, andcabling is used to connect two processor modules [point to point] orsmall number of processor modules that are part of a larger assembly ofprocessor modules. All of the backplane or cabling interconnectionmethods presently in use in such systems, due to their physicalstructure or size, are not practical or are impossible for use in makinghigh numbers of point-to-point connections per processor module, andfurther, to the extent that they are used result in a significantincrease in the overall physical size or volume of the system. It isbecause of the physical or mechanical limitations inherent in the wiredinterconnection methods used for interconnecting processor modules thatsystems of processor modules are organized in groups of processormodules that are in some fashion closely coupled or interconnected andwherein the number of processor modules in a group is typically lessthan 32. Groups of processors are loosely coupled or interconnected bycabling to make data processing or supercomputer systems consisting ofmore than the number of processor modules that may be in a group ofprocessor modules.

An example of such a data processing system is a current IBMsupercomputer of 1,408 processors consisting of 44 groups of processorswherein each group contained 32 processors; computational systems likethis IBM supercomputer presently cost in the hundreds of millions ofdollars even though the microprocessor and memory ICs comprising amajority of the data processing related ICs in their assembly amount toless than 1% of their cost. The majority of the physical costs of suchlarge computational and communication systems are accounted for by thecosts of their PCB and cabling interconnections and not thesemiconductor ICs. This disparate distribution of the material costs ofthe system has the result, which is well known to those skilled in theart of designing large multiple processor computational systems, likethe above referenced IBM super computer, that the number ofinterconnections per processor module is not sufficient to allow theprocessors to operate continuously at peak performance.

An alternative interconnection structure architecture to processormodules organized as groups, sub-arrays or clusters such as the IBMsupercomputers is the mesh or Massively Parallel-Processing [MPP]interconnection structure used in the Red Strom supercomputer system ofCRAY Inc. wherein over 10,000 microprocessor modules are physicallyinterconnected each to seven other microprocessors. When a processormodule needs to communicate to a processor module that it is notphysically interconnected, router logic in each module routes or passesthe request and information to subsequent intervening processor modulesuntil the target processor module of the communication is reached. Thisis similar to an Internet Protocol communication network whereincommunication between the majority of processor modules is not a directpoint-to-point interconnection, but through some number of interveningprocessor modules with an additional access and transmission delay foreach intervening processor.

It is clear that both the clustered and mesh processor moduleinterconnection topologies are not uniform point-to-point topologies.Both of these currently in use processor module interconnectiontopologies are known to excessively limit the maximum potentialperformance of the system of processor modules due to delays resultingfrom data transmission paths with intervening or forwarding modulesduring communications between various pairs of processor modules.Further, due to the fixed and physical interconnections connecting theprocessor modules, when a physical failure occurs that affects the useof one of these fixed and physical interconnections or when there iscommunication along a specific fixed capacity interconnection path thatexceeds its capacity, routing around or avoiding this failed or capacitylimited interconnection path has as yet to be solved without resultingin additional performance losses and system implementation costs. Theselimitations are a direct result from the fact that the interconnectiontopologies of these processor module structures do not use a multiplepoint-to-point interconnection method and that physical and not wirelessinterconnection methods are used.

The limitations of present processor module interconnection technologyused in the design of large computational or communication systems canbe summarized as three broad categories:

-   -   1. Processing capacity. The processing capacity of a system of a        large number processors operating in parallel for the processing        of a common problem is directly related to the structure of the        interconnections interconnecting each of the processors and        physical distance separating each of the processors.    -   2. Interconnection capacity. The interconnection capacity of a        system with a large number or array of processors used in        parallel for the processing of a common problem is directly        related to the number and available on demand [instantaneous]        capacity interconnections interconnecting each of the        processors. This interconnection capacity also directly affects        the capability of such processor systems to recover from        physical failures and excessive interconnection path loading.    -   3. Physical size or volume. The greater the number of physical        interconnections interconnecting each of the processors of a        system of processors the greater the physical size or volume of        space required by the interconnection means and the greater the        separation distance between each of the processors. The physical        size of the mechanical means used to interconnect processor        modules such as PCB backplanes and cabling connector sockets        require a physical volume of space for their use that is        considerably larger than the volume of the ICs they are intended        to interconnect. This volume of space for wired interconnections        for a module is greater by factors in a range of 1,000 to over        100,000 than the volume of space required by the processing        electronics they are intended to interconnect.

The VSI invention enables a means for reduction of the cost andperformance disadvantages presently resulting from high densities ofphysical interconnections between information processing or switchingplanar ICs, VSI ICs or stacked ICs also from time to time hereinreferred to as a processor ICs, or modules of VSI ICs or stacked ICs andor planar ICs, wherein a module also from time to time herein referredto as a processor or processing module, is a collection of such ICs onone or more interconnection substrates; examples of modules are a MCM[Multi-Chip Module], MCP [Multi-Chip Package], a PCB [Printed CircuitBoard] with ICs or MCMs thereon and an assembly of PCBs. The preferredembodiment of this example of the VSI invention is a VSI IC modulewherein in one or more VSI ICs integrate one or a plurality of wirelesstransceivers as circuit layers of the VSI IC stack for creating awireless interconnection and enabling communication between one or moreother such VSI IC modules, however, such a module is not limited to orby the use of a VSI IC; the module would also incorporate the antenna orantennas required to enable a means of transmission of the wirelesssignal. The antenna can be fabricated as part of a VSI circuit layer ina VWM, or as part of a substrate one or more VSI ICs are bonded andincorporated in a VWM. Herein this processor module will be referred asa VSI wireless module, VWM, or from time to time a processor module ormodule. The VSI wireless module or VWM is not limited in data processingcapability or memory storage capacity. VWMs can be used for example inthe assembly of data processing systems, servers, IP network switchingsystems or supercomputers. VWM systems are preferably enclosed by anenclosure which shields or prevents the release of electro-magneticradiation in the Mhz, Ghz or Rf [Radio frequency] frequencies from VWMsand prevents the entry of such interference radiation frequencies; theuse of this radiation shield is optional and depends on the use of theVWM system.

A VWM in addition to incorporating one or more wireless transceivers canincorporate a wide range of data processing capabilities and dataprocessing logic capacity. Examples of the various logic circuits a VWMcan incorporate singularly or combination are one or moremicroprocessors such as 32 or 64 bit fixed instruction microprocessors,programmable logic such as FPGAs [Field Programmable Gate Arrays],custom design logic such as ASICs [Application Specific ICs]. A VWM canincorporate most of the various types of integrated circuit memorytechnologies such as SRAM, DRAM, Flash, ferroelectric, MRAM,chalccogenide based memory cells or dendritic based memory cells, and incapacities of a few thousand bytes to more than several gigabytes. Inthe preferred embodiments of a VWM, there is a memory capacity fromseveral megabytes of memory to more than sixteen gigabytes of memory. AVWM can incorporate one or more wired bus interconnections, however, inthe preferred VWM embodiment there is only one bussed interconnection orthere are none; such VWM wired interconnections, either electronic oroptical, are typically arbitrated or shared bused connections common toa portion or all the VWMs of the system in which they are incorporated.

A VWM by intention has a limited number or no wired connections for datatransmission to other VWMs. The wireless transmission between VWMsenables the forming of multiple point-to-point or VWM to VWMtransmission paths as needed and or on demand such that all connectionpaths are effectively a nearest neighbor connection; the transmissionpaths and the number of point-to-point transmission paths between VWMsare dynamically configurable under VWM programmed control, this isclearly not possible in a wired system of data processing modules. Thepreferred embodiment of the VWM invention is VSI IC incorporating aplurality of wireless transceiver circuits within its circuit layers andwhere each transceiver is preferably programmable to a plurality oftransmission frequencies. The programmable transmission frequencies arepreferably in the Radio frequency [Rf] frequency range. A VWM also maybe an assembly of more than one VSI ICs and conventional planar ICs. Theobjective of the wireless interconnection [communication] between anytwo VWMs is to provide one or more point-to-point high speed highcapacity data transmission paths at one or a plurality of transmissionfrequencies. The use of multiple transmission frequencies simultaneouslyenables higher overall data transmission through parallel transmissionof information or data as a means to achieve greater bandwidth. Thesignal strength of the wireless interconnection signal between VWMs needonly be sufficient to reach any one of the other VWMs in a specificsystem assembly or array of modules where the maximum wirelesscommunication distance between modules of such an assembly or array mayvary in a range from less than an inch to less than 10 meters and withthe nominal or preferred distance being less than 4 feet and less than18 inches wherein the use of lower Rf radiated power per VWM transceiveris an embodiment preference. The localized use or limited distance useof the wireless interconnection signal in combination, if necessary,with radiation shielding allows any MHz or GHz frequency to be usedwithout causing interference with the licensed transmission frequenciesin use such as those used in cellphones or TV transmissions. Theradiation shielding is made with conventional methods as a metallicgrill or solid metallic layer or film and with the appropriate choice ofmetal. The use of a radiation shield enclosure enables the use of thegreater range of transmission frequencies by a system of VWMs withoutregard to the use of those transmission frequencies that are reservedfor licensed use such as broadcast frequencies. The radiation shield canbe used to reduce the signal noise within the space it encloses, andtherefore, among the VWMs it encloses, by absorbing incident radiationand so reducing reflected signal radiation from the VWMs.

Power to a VWM may also be wirelessly transmitted. This would allow anarray of VWMs to be embedded in a large electronic and or mechanicalassembly or system without physical wiring connections. The use ofwireless power transmission to a VWM depends on the power requirementsof the VWM or VWMs to be used and the type of transmission methods usedsuch as a conventional isotropic antenna transmission or adaptiveantenna transmission. VWMs that are powered through wireless transmittedpower, in their preferred embodiment would incorporate a rechargeablebattery.

A transceiver in a VWM uses one or more antennas incorporated in the VWMto transmit a wireless signal to one or more VWMs in a VWM array or toone or more VWMs in another VWM array, or to information or datareceiving electronics that can be internal or external to the system inwhich the transmitting VWM is installed. The preferred VWM antennaembodiment is an adaptive array antenna for the purpose of achievingspatial transmission path spectrum or channel reuse among VWMs of a VWMarray. The adaptive array antenna is presently used in cell phonecommunication networks to maximize the use of Rf frequencies availableto the cell phone service provider. The VWM use of adaptive arrayantennas is in a much different manner than their present use by cellphones; whereas cell phones communicate only with and through a centraltransmission tower, VWMs communicate directly with one or plurality ofVWMs without an intermediate transceiver means. VWMs use adaptiveantenna technology to enhance the capability to achieve on demandtransmission paths for direct simultaneous communication to one or moreother VWMs, and therefore, without an intermediate transceivercoordinating or controlling means. Although the use of an intermediatetransceiver means such as a central switching or control point tower asthat used in the structure of cell phone communication could be used,this approach is not necessary and would add delay to transmissionperformance. This is the case because each VWM in a VWM array is held ina fixed position relative to the other VWMs of the array without arequirement for tracking VWM movement or coordinating its availabilitystate as in a cell phone communication network; the position of one ormore VWMs can be changed during its operation as might be the caseduring maintenance and this can be dynamically compensated by theaffected VWMs, however, VWMs are not expected to be individually mobilelike cell phone users. The communication network of a VWM array in itspreferred embodiment is self organizing upon startup and continues to beso during operation, wherein each VWM of the array is identified toevery other VWM of the array and a determination of the physicalposition of each VWM relative every other VWM of the array is made suchthat the adaptive antenna electronics of each VWM can create a spatialtransmission path to the adaptive antenna of every other VWM of the VWMarray. If an established spatial order of VWMs is changed or disrupted,a new spatial order would be computed, however, this is not expected tobe a frequent occurrence.

The objectives in using a wireless interconnection for theinterconnection structure of a VWM array are data transmissionperformance with the characteristics of non-interfering point-to-pointtransmission using whatever transfer protocol that provides for thehighest level of reliable information or data transfer rate and minimumaccess delay. This is markedly different from most applications ofwireless data transfer such as in a cell phone for at least two reasons:first, the wireless interconnections formed between two VWMs aredesigned only for data transmission between VWMs in much the same way adedicated wired interconnection between two VWMs would be designed andwithout the design restraint of compliance with one or more establishedtransmission standards or protocols over the relatively short distancesbetween VWMs of preferably less than one meter [39.4 inches]; andsecond, due the preferably small volume of a VWM array, the environmentof a VWM array is preferably closed or shielded and not subject toexternal radiation interference sources normally found in an open air orunshielded environment and is preferably not intended for communicationdirectly with public communication systems.

VWMs can use multiple Rf frequency bands in order to increase thetransmission of information or data between two VWMs, and to allow thedirect simultaneous transmission of data by a VWM to two or more otherVWMs. The use of adaptive antennas by VWMs is the preferred transmissionmeans although it is not essential to the implementation ofpoint-to-point transmission paths between VWMs. The preferred Rffrequencies used by VWMs are in the range of 10 Ghz to 300 Ghz, but notlimited by this range. The choice of frequency bands to be implementedby the VWMs of a VWM array is determined primarily by the availabletransmission rate of the frequency band through the various materialsused to make the VWMs and mechanically suspend them in their arraystructure with respect to non-line-of-sight transmission, and the sizeof the antenna or antennas needed for effective transmission at theselected frequency band or bands. For example, the length of an antennais determined by the wavelength of the central frequency of a frequencyband, the wavelength of a 1 Ghz frequency is 300 mm [11.8 inches], thewavelength of a 60 Ghz frequency is 5 mm [0.1968 inches] and thewavelength of a 100 Ghz frequency is 3 mm [0.1181 inches]. It is clearfrom the above examples of wavelength with respect to Rf frequency thatthe use of higher frequencies allows for the fabrication of smallerantennas for each VWM and the antenna is preferably fabricated as anintegrated part of the VWM.

VWMs can vary significantly in processing capacity, functionalcapability, storage capacity and wireless communication or transmissioncapacity, more commonly referred to as information or data transmissionbandwidth. This is to say that system assemblies of VWMs can beheterogeneous or can have specialized functions such as IP [InternetProtocol] processors, data base analysis processors or conventionalgeneral purpose instruction set processors, however, the wirelessinterconnection or communication transceivers of the VWMs of a systemare by necessity compatible, thereby providing high speed dynamicallyconfigurable [changeable under programmable control] module to moduletransmission paths for information or data transfer without therestrictions imposed by wired interconnections of fixed and unchangeablephysical connection paths between communicating processor modules or thevolume required for these physical interconnection such as sockets formechanically coupling the wired connections to each module. A VWM mayincorporate one to 1,000 to over 4,000 wireless transceivers, this isenabled as a direct result of the circuit stacking capability of the VSIinvention. Further, since each wireless transceiver of a VWM may beprogrammed on demand to transmit to any of the VWMs in an array of VWMs,the cost of the interconnection communication path is clearly limited tothe cost of the IC transceiver circuitry no matter which two VWMs in asystem array of VWMs of any size need to establish a transmission pathbetween each other for the transfer of data or information. This is incontrast to current wired connections where a physical connection pathbetween any two modules must previously exist to affect the transfer ofinformation. Further, for each physical or wired connection there is therequirement for a socket or connector into which the wiring means mustbe mechanically plugged in order to form a wired connection. A wireddata processing module requires such a connector means for each physicalor wired data transmission path it may incorporate; the number of wireddata transmission paths of a wired module is limited by at least thephysical volume need for such connectors. The elimination of thephysical or wired connection path [of either electronic or opticalmeans], and therefore, their physical and mechanical limitations is aprincipal benefit and advantage to a data processing equipment or systememploying an array of VWMs.

The data transmission paths between VWMs may be dynamically established.This means that the wireless transceivers of a VWM can be used toconfigure the information or data transmission interconnection topologythat is best suited for a particular information or data processingtask, and subsequently reconfigured to the requirements of anothertasks. It is the capability for on demand point-to-point interconnectionof VWMs in any as needed order or arrangement of interconnection withoutrequiring an intervening physical [electronic or optical] switching orforwarding means, or preexisting wired interconnection capacitysufficient to provide transmission between any configuration ofinformation or data processing modules, that provides a novel size[volume], performance and cost advantage of a system of VWMs versus asystem of wired modules. It is because of the physical volume andmechanical connection forming requirements of systems of wired modules,that the modules of such systems use one or a few shared or commoninterconnection transmission paths or buses typically fabricated in theform of PCB backplane into which wired modules are plugged. It is thephysical volume and mechanical connection forming requirements that makepoint-to-point transmission path topologies for systems of wired modulesimpractical or impossible for systems consisting of more than 8 to 16wired modules. The wireless transceivers and antennas of the VWMinvention replace the function of the high performance PCB backplanesand other PCB and cabling interconnection means while increasingprocessor interconnection capacity and reducing system interconnectionimplementation costs.

It should be further noted that a VWM array is an inherently fail safecomputing structures. What is meant by this, is that in the event of thefailure of a VWM, the VWM array prevents the use of a failed VWM byperforming similar computing processes to those used for establishing orverifying wireless transmission paths between VWMs such as when the VWMarray is first started. Continuous reconfiguration processes eliminate,preferably through self adaptive and decentralized VWM function, thefailed VWM from use within the VWM array, or more simply said, byreconfiguring the existing wireless transmission paths of the VWM arrayto exclude the failed VWM. This fail safe capability is a by productresulting from a VWM array or system with decentralized VWM selforganizing capability and is inherent in an assembly of wirelessprocessing modules where all connection paths are effectively a nearestneighbor connection.

FIG. 11D shows an array of eight [8] VWMs 11 d 1 through 11 d 8 with Rfsignal communications 11 d 9 a and 11 d 9 b between each of thesemodules and an optional electronic shield 11 d 10 enclosing the VSImodules to prevent the electro-magnetic radiation of the Rf signals fromthe VWMs from potentially interfering or harming electronic equipment insufficient proximity to the VWM array or for external Rf signals fromreaching the VWMs of the array. Power interconnections between the VWMsare not shown for simplicity, but also with consideration that the VWMscould be wirelessly powered if so designed; the Radio frequency [Rf]transmission of power to electronic ICs is well known in the art, andtherefore, no discussion is provided. The wireless communication pathsare shown as being line-of-sight 11 d 9 a and non-line-of-sight 11 d 9b; the as indicated wireless transmission paths 11 d 9 a, 11 d 9 b shownin FIG. 11D are for illustrative purposes only and are not intended tobe exhaustive or limiting by their presentation of a VWM wirelessinterconnection network. Not all transmission frequencies that could beused for wireless communication between VWMs will provide the capabilityfor forming a non-line-of-sight information or data transmission path,but the capability of non-line-of-sight frequency transmission when usedallows electronic systems formed by the aggregating or arrangement orassembly of three dimensional [3D] arrays of VWMs as shown in FIG. 11Gwherein some number of VWMs in a 3D array do not have a line of sightbetween each other but are not restricted from forming point-to-pointcommunication information or data transmission paths.

It can be seen from FIG. 11D that each of the eight [8] VWMs has adirect point-to-point interconnection to each and every other VWM in thearray of VWMs. In a preferred embodiment of a VWM array each VWM wouldhave a plurality of wireless transceivers with unique transmissionfrequencies or adaptive antenna electronics such that each VWMs couldhave an interconnection transmission path to each of the seven otherVWMs that would permit non-interfering simultaneous transmission ofinformation to any VWM at any time, if greater bandwidth between eachmodule were required additional transceivers at unique frequencies couldbe added, thereby creating a number of parallel interconnection pathsbetween each VWM. However, it is not necessary for each VWM to have aseparate transceiver for each of the other VWMs of an array, but atleast one is required and as few as one or two transceivers will besufficient to satisfy the communication requirements of some VWM arraysand allow non-arbitrating non-interfering point-to-point communication.It is through the addition of wireless transceivers per VWM that theinformation or data bandwidth between any two modules can be increasedwithout a corresponding increase in physical size of the VWM as would bethe case of a wired module. It is also the case that for a fixed numberof transceivers per VWM, the number of VWMs in a VWM array can beincreased without diminishing the processing throughput of the VWM arrayfor the fundamental reason that for most information processing tasksthe number of communication paths needed simultaneously by a VWM is arelatively small number that is generally four [4] or less, however, theVWMs connected by these communication paths can vary greatly and may atany time be between any two of the VWMs in the VWM array; further, thesewireless communication paths between any two VWMs are non-interfering orexclusive to the VWMs using it and not shared or multiplex with otherVWMs. Therefore, for these reasons, the number of VWMs in an array canbe increased without a decrease in interconnection bandwidth or anincrease in the number of potential I/O interconnections per VWM. Theability of each VWM in an array to create a non-interfering transmissionpath to any other VWM of the array on demand results is a capability ofVWM arrays that could be equaled in wired systems only by having aphysical connection between each and every other module in a wiredsystem resulting in an increase of the physical size of the wired systemof at least one to two orders of magnitude for wired systems of thirtytwo [32] or more processor modules without consideration of whether suchimplementations are cost effective or even possible.

The numbers of VWMs in an array can be increased with a proportional orlinear increase in physical size or volume. This is the case becausethere is no increase in VWM size due to the increase in potentialwireless interconnections, the circuitry in the VWM or any additionalincrease in such circuitry as layers in a VSI IC circuit stack, sincethe addition of VSI circuit layers does not necessarily result in anincrease in the overall volume of the VWM. Further, because theassignment of transmission frequencies are programmable or can beallocated on demand, a module may simultaneously broadcast informationto more than one module using the same frequency, while wirelessinterconnection capacity for other on going uses is not affected. Itshould be pointed out that there is a very large number ofinterconnection structures that can be programmed between VWMs toachieve an optimized interconnection performance implementation for eachof the may widely varying information or data processing applicationsthat currently exist. This flexibility of the formation of on demandinterconnection paths between information or data processing modules of,for example, multiprocessor severs, is not possible because eachprocessor has a fixed wired connection structure. Further, currentmultiprocessor systems use one or more wired bus interconnections[electronic or optical], these interconnections are shared or in commonconnection and must be arbitrated between the attached processors inorder to obtain their use. It is well know in the art that such sharedbus interconnections greatly reduce the operating performance of theprocessors that use it due to the transmission bandwidth limitationsattributed to a shared bus.

The physical volume of the preferred embodiment of a VWM is 1 cubic inch[16.387 cm3], however, a VWM can be larger or smaller in volume. Thesmaller the size of a VWM, then the greater the number of VWMs per unitvolume resulting in smaller equipment size, and the shorter thetransmission distance between VWMs providing increase equipmentperformance.

In the preferred embodiment of a VWM array the position of each VWM inthe VWM array is in a fixed position relative to the other VWMs of thearray it is embedded while it is in operation. Fixing the position ofeach VWM in an array permits the point-to-point wireless transmissionsignals between each VWM to be characterized or to be tuned for optimumtransmission performance with the assumption that the geometry of itsenvironment with respect to the position of other VWMs is not variable.It is not a requirement of the invention that each VWM of a VWM array beheld in a fixed position in order to be functional, however, it ispreferred because it simplifies the typical operation of each VWM whileincreasing throughput. It may also be an operating requirement of a VWMsystem that there be a limited capability to change the position of VWMswithout interruption of its operation. This requirement is the case forapplication such as life critical support or 24 hour transactionprocessing systems, and are referred to as high availability or non-stopelectronic systems.

It is well known in the art that for computing or data processingsystems or supercomputer systems that are made of large numbers ofmicroprocessors, that it is the wired interconnection structureinterconnecting the microprocessors that is more than half of the costof the electronics making up such equipment and is the primarydeterminer of its performance. It is well known that currentmultiprocessor sever, parallel processor systems or supercomputersystems which use large numbers of microprocessors such as 8 to severalthousand are required to use some form of shared bus system as afundamental implementation requirement in order to implement a means ofcommon interconnection structure between all the processors, however,there presently appears to be no wired interconnection structure forlarge numbers of processors that provides a direct nearest neighbortransmission path for all processors of a system or where the order ornumber of those transmission paths is without restriction. It is wellknown that dedicated wired, non-shared, non-interfering point-to-pointinterconnection between information processing modules is the simplestand most throughput efficient interconnection means, but rapidly becomesimpractical to implement for large numbers of microprocessors or theelectronic module of a microprocessor or microprocessors. The number ofprocessors used in supercomputers presently made by IBM, Hewlett-Packardor NEC exceed 1,000, however, these supercomputers are structured intosubsystems comprising typically 32 processors or less; these processorsubsystems use backplane interconnection structures which provide one ormore common or shared or multiplexed connections between all theprocessors in the subsystem, continuously or on demand availablepoint-to-point interconnection structures are not known to be used. FIG.11D shows a wireless point-to-point interconnection structure of aminimum of 28 point to point wireless interconnection paths 11 d 9 a, 11d 9 b between eight [8] VSI wireless modules resulting in a total ofpotentially 56 separate serial module interconnection or transmissionpath transceivers.

The complexity of a wired point-to-point interconnection structure[often referred to as a star or radial interconnection structure] can beunderstood from FIG. 11D should the wireless paths be replaced by wiredpaths and with each wired path having a wired width of 32, 64, 128 or256, which are often the width of data paths [bus widths] used incomputers from desktop PCs to high performance servers andsupercomputers. The wired interconnection connectors of each processormodule and physical cabling require a volume several times that of themicroprocessor modules, and because of this volume increase theseparation distance between the modules results in lower performance andor increased power requirements necessary to drive the signals due tothe length of the interconnection. However, most importantly, the costin parts and assembly of such a wired interconnection structure exceedsthe cost of the microprocessor electronics of the processor modules. Itbecomes clear that electronic equipment consisting of 64 microprocessormodules and using a point-to-point interconnection structure wouldrequire 2016 separate wiring or cabling connections and 256microprocessor modules using a point-to-point interconnection structurewould require 32,640 separate wiring or cabling connections; each suchwiring or cabling connection may consist of a single physical wire oroptical fiber or more likely a wiring bundle of 32 or more wires. It isclear from these examples that the use of a point-to-pointinterconnection structure, or variations thereof, for interconnectingeight or more microprocessors rapidly becomes an implementation methodthat is physically daunting or not possible despite its performanceadvantages.

What the VSI wireless module array invention enables is the use of theeconomies semiconductor integration manufacturing to effectivelyintegrate the external physical interconnection structures betweenmicroprocessor or electronic processor modules into the module. Theresult of this integration is a reduction in the size, power andmanufacturing cost to implement electronic equipment using a pluralityof microprocessor modules. The integration of wireless transmission intoa VSI IC or a circuit stack represents a manufacturing cost that issubject to the well known and established cost reduction efficiencies ofsemiconductor manufacturing of approximately 40% per year, whereas, thecost of any physical wiring interconnection means enjoys no suchcomparable year to year cost reduction benefit, but are seen asnon-reducible and fixed manufacturing costs. The VSI invention enablesthe effective integration of interconnection paths onto the VSI IC, andin doing so achieving benefits of reduced cost and increased performanceof the interconnection paths between VWMs or information processingmodules.

The larger the number of processor modules in an information processingsystem or subsystem, the greater the probability of failure in anelectronic component of a processor module or the connectors that jointhe processor modules to backplane or cabling. The well establishedreliability benefits of semiconductor integration are offset by theincreased part counts of larger electronic systems that have large partcounts. The VSI wireless module reduces the part count of a large systemto approximately the number of VSI wireless modules used. An example ofan application using a large number of VSI wireless processor modules isshown in FIG. 11E. In FIG. 11E VSI wireless processor modules 11 e 11through 11 e 1 m and 11 e 21 through 11 e 2 n are interconnected bywireless point-to-point transmission paths 11 e 4 and an optional commonwired cabling path 11 e 5; the as indicated wireless transmission paths11 e 4 shown in FIG. 11E are for illustrative purposes only and are notintended to be exhaustive or limiting by their presentation of a VWMwireless interconnection network. The part count of this system based onthe VSI invention can be seen as approximately [m+n] modules, [j] I/Oprocessing modules 11 e 31 through 11 e 3 j and cabling 11 e 5 plusconnectors [not shown]. The system is optionally enclosed by radiationshield 11 e 6 to reduce wireless transmission interference. FIG. 11Eshows that the transceivers of the wireless transmission paths arepoint-to-point and the bandwidth of any point-to-point wireless path isdetermined by amount of wireless circuitry integrated into the VSI ICsof the wireless processor modules; this is intended to be example of howthe VSI invention increases the level of IC integration of the system byreplacing or integrating what would normally be interconnectionstructure consisting of physical cabling, connectors and line drivercircuitry into lower cost, lower power integrated circuitry of a VSI IC.The number of processor modules [m+n] in FIG. 11E could easily exceed 32without a reduction in wireless communication performance due todeficiencies in interconnection bandwidth since the performance of theinterconnection between the VSI wireless processor modules is notdetermined by the wired interconnection 11 e 5 but by the numerousindicated wireless interconnections 11 e 4. The incorporation of thewired interconnection 11 e 5 of FIG. 11E is optional and could beeliminated; since it is shared over a large number of processor modules,it is not likely that it would be used for performance criticalprocessing, but it could be used as a system management or maintenanceresource. Modules 11 e 31 through 11 e 3 j with wired I/O connections 11e 31 c to 11 e 3 jc are also wirelessly connected to the VWMs and serveas interfaces to external peripherals or connections.

The preferred embodiment of a VWM computing system or a VWM array doesnot incorporate a backplane or physical wiring interconnect means. If abackplane or wiring interconnection means is used, it is not used as theprimary interconnection or busing means for transfer of information ordata. FIG. 11E and FIG. 11F show wired interconnections means 11 e 5, 11f 31 c, 11 f 41 c these are used as examples of how wiredinterconnections could be used in conjunction with wirelessinterconnections discussed herein, however, the wired interconnectionmeans in the preferred embodiment of a VWM system is not the primaryinterconnection means.

FIG. 11F shows an IP [Internet Protocol] communication processing switchand router consisting of I/O processing VWMs 11 f 11 through 11 f 1 jand 11 f 21 through 11 f 2 k and IP message information or dataprocessing VWMs 11 f 31 through 11 f 3 m and 11 f 41 through 11 f 4 n.The I/O processing VWMs have one or more each of wired interconnection11 f 11 c through 11 f 1 jc and 11 f 21 c through 11 f 2 kc. Each of theinformation or data processing VWMs may optionally incorporate one ormore wired interconnections 11 f 31 c, 11 f 41 c that interconnect incommon two or more VWMs, Wireless transmission paths 11 f 51, 11 f 52are point-to-point interconnections between the I/O processing VWMs 11 f11 . . . 11 f 1 j, 11 f 21 . . . 11 f 2 k and IP message information anddata processing VWMs 11 f 31 . . . 11 f 3 m, 11 f 41 . . . 11 f 4 n; theas indicated wireless transmission paths 11 f 51, 11 f 52 shown in FIG.11F are for illustrative purposes only and are not intended to beexhaustive or limiting by their presentation of a VWM wirelessinterconnection network. Further, wireless transmission paths can bemade between the various I/O processing VWMs and between the various IPmessage information and data processing VWMs. An optional radiationshield 11 f 6 is used to prevent radiation from the transmissions of theVWMs from going beyond the radiation shield or allowing radiation frombeyond the radiation shield from reaching the VWMs.

The IP communication processing switch and router of FIG. 11F isintended to perform similar operations to those of existing IP routerand switching equipment but without the well known physical wiringbandwidth limitations between I/O electronics and IP message processingelectronics. IP messages are received through wired interconnections,sent to an IP message information and data processing VWM fordesignation determination and then sent on to the appropriate I/Oprocessing VWM for transmission over wired interconnections. It is wellknown that IP message traffic loading through IP switching equipment canvary widely and unpredictably and that having sufficient IP messageprocessing and transmission data path capacity to handle such changingIP message loads has proved challenging in the design of this type ofelectronic equipment using wired interconnection paths. The IPprocessing equipment of FIG. 11F provides the novel capability ofdynamically configuring IP message processing capacity and bandwidthcapacity by use of reconfigurable wireless transmission paths betweenthe I/O processing VWMs and the IP message processing VWMs. The wirelesstransmission data paths 11 f 51, 11 f 52 do not have to be line-of-sightpaths. The IP message processing capacity of the invention can beincreased with the addition of IP message processing VWMs withoutconsiderations for the ability of each VWM to accommodate an increaseddensity of interconnection paths or the increased physical space thatwould be required for wired interconnection. The IP communicationequipment of FIG. 11F has the novel capability for using more VWMs toprocess IP messages in parallel in an on demand capacity basis withoutconsideration of whether the system will have sufficient messagetransmission or switching capacity. This is a result of the use ofwireless interconnections which can be increased between various VWMs asneeded through the reconfiguration of transmission data path and thetransmission frequencies used between any two VWMs and the use of moreVWMs to maintain a level of performance which is termed in the industryas “wire speed” or the processing of IP messages at the speed at whichthey arrive at the equipment without a throughput wait or delay in theirprocessing. The IP message processing capacity of the equipment is notlimited to the structure of VWMs 11 f 31 . . . 11 f 3 m, 11 f 41 . . .11 f 4 n, but can take on other structures such as that shown in FIG.11D or FIG. 11G for example. The invention uniquely enables allocationof VWM IP message processing and transmission capacity and capabilitywithout the requirement that the VWMs be designed in advance toanticipate such allocations as must be done in the case of wiredsystems.

VWM arrays can be arranged in three dimensional structures in additionto the planar structures as suggested by FIG. 11D, FIG. 11E and FIG.11F. This enables the emergence of a new form of three dimensional ICintegration wherein VWM are closely packed into the shape of varioussolid 3D geometric structures or arrayed in the outline of hollow 3Dgeometric structures such as a cube or a sphere. FIG. 11G shows apictorial view of an array of VWMs in a cubic 11 g 2 structure. FIG. 11Gshows wireless transmission paths 11 g 42, 11 g 41, 11 g 43, intended tosuggest point-to-point transmission data paths between all VWMs of the3D VWM array and between all VWMs of the 3D VWM array and two externalinterface processing modules 11 g 1, 11 g 3 within wireless transmissionradiation shield 11 g 5 and with external I/O wired connections 11 g 1c, 11 g 3 c; the wireless transmission paths 11 g 42, 11 g 41, 11 g 43as indicated in FIG. 11G are for illustrative purposes only and are notintended to be exhaustive or limiting by their presentation of a VWMwireless interconnection network. Each VWM of the cubic 11 g 2 structureis interconnected with point-to-point wireless transmission paths 11 g42. These wireless transmission paths 11 g 42 are a combination ofline-of-sight and non-line-of-sight transmission paths. The wirelesstransmission paths shown 11 g 41, 11 g 42, 11 g 43 represent one or agroup of transmission frequencies depending on the desired data pathwidth or the desired data transmission rate between VWMs. The cubicarray of FIG. 11G is shown as comprising 64 homogeneous or heterogeneousVWMs without wired interconnections; wired power distribution to theVWMs is not shown. Each VWM of the VWM array 11 g 2 is not restricted inthe number of wireless transmission path capacity it may have but it isnot necessary for each VWM to have sufficient wireless capacity suchthat each VWM be capable to simultaneously communicate with each of theVWMs of the array, however, such simultaneous communication capability,if needed, can be accomplished through integration of greater numbers ofwireless transceivers. The capability for any VWM of the VWM array 11 g2 to form a wireless interconnection to some number of other VWMs is arequirement only of the transceiver capacity of the VWM and not acapacity limitation inherent in the design of the size of the VWM arrayor other system level design consideration.

It is clear from FIG. 11G that the VWM array of 64 VWMs is a closelypacked 3D structure which is not complicated by wireless interconnectioncircuitry or antennas required to implement the large numbers ofpotential wireless transmission paths that may exist at any one momentin time, nor does the physical size or volume of the array have tocompensate for the wireless circuitry required for creating thetransmission paths between each VWM. This is to say the physical size ofan individual VWM is largely independent of the size of a VWM array ofwhich it is in, such that the size of a VWM array can be increasedwithout diminishing the point-to-point connectivity between the VWMs ofa VWM array as the size of the VWM array is changed. Further, if thenumber of VWMs of the array were increased from 64 to 256, 1000, 8000,20,000 or some other large number, the volume of the VWM array wouldincrease as a multiple of the average volume of the VWMs used in thearray, and not require an increase in the size of the individual VWM inorder to accommodate the increase in the number of interconnectionsrequired to interconnect to a larger number of VWMs. This is unique tothe VWMs wireless method of VWM to VWM interconnection when compared toa wired multiprocessor or cluster system with point-to-pointinterconnection wherein the addition of a processor would require theaddition of wired interconnection couplings to each of the existingprocessors of the system.

A VWM computing system or VWM array enables the reduction of thedistance necessary for information signals or data to travel betweenVWMs. More than approximately 50% of the delay in sending a signalbetween logic modules in conventional systems is due to the wireddistance between them, the VWM array capability to closely space theVWMs reduces the distance signals must travel between VWMs versusconventional logic modules by 5× to more than 100×, and in considerationof some large multiple processor or supercomputer systems, more than1000×.

A VWM computing system or VWM array enables fault tolerant capacity andexcessive transmission path loading recovery through programming changesof the VWMs. This is novel to the VWM due to its wirelessinterconnection means. Fault tolerance can be implemented in a VWMsystem through isolation or reconfiguration of the available or useablewireless transmission paths of the VWM array by software programmingmeans to avoid a physical failure at a VWM as it occurs. Excessivetransmission path loading between any two VWMs is avoided byreconfiguration or reallocation by software programming means of theavailable point-to-point transceivers of the affected VWMs to createadditional or multiple point-to-point transmission paths to increase thetransmission capacity between the capacity affected VWMs.

Another aspect of the use of a VWM is in an unshielded network. In thisaspect the preferred embodiment of the VWM is to have a volume of lessthan ten [10] cubic inches, preferably less than four [4] cubic inchesand preferably less than one [1] cubic inch, water proof packagingwithout external contacts, powered by wireless transmission with orwithout an internal battery, made from one or a plurality of VSI ICssuch as those shown in FIG. 3 through FIG. 6, and where a VWM operatesover regulated transmission frequencies or over a sufficiently shortlegally proscribed distances for unregulated frequencies so that noharmful or interference effects result from VWM usage. Further, in thispreferred embodiment of the VWM, the VWM may communicate wirelessly overconventional or standard wireless communication protocols andfrequencies to non-VWM electronic equipment, be used by itself or with aplurality of other VWMs, and where a VWM may have dedicated functionssuch as mass storage, audio or video processing, for consumerappliances, home security and networking control, home appliancecontrol, cell phone and wireless phone networking, or applicationspecific processing functions such as language translation, voicerecognition or handwriting recognition. These VWMs, like the VWMs of aVWM array previously discussed, are capable of forming self organizingwireless networks with multiple transmission paths to multiple VWMs orbetween any two VWMs with those VWMs that are in sufficient proximity.

Benefits of an information or communication processing VWM array:

-   -   1. Dynamic or on demand availability or configuration of        VWM-to-VWM interconnections.    -   2. Dynamic reconfiguration of VWM-to-VWM data path bandwidth        enabling the increase or decrease transmission path bandwidth        capacity as required.    -   3. A physical increase or decrease in the number of VWMs in a        VWM array by more than 25% without requiring physical changes to        the connectivity between VWM.    -   4. System or equipment physical size or volume reduction through        the reduction or elimination of wired interconnection connectors        and cabling between VWMs.    -   5. System processing throughput capacity increase through the        reduction of the physical transmission path length separating        point-to-point VWM interconnections.    -   6. System assembly cost reduction through reduction or        elimination of wired interconnection connectors and cabling        means interconnecting VWMs.    -   7. System processing capacity characterized by using VWM-to-VWM        or point-to-point transmission structure for all VWMs in a VMW        array regardless of the number of VWMs in the VWM array.    -   8. System recovery from physical failures of the electronics in        a VWM through isolation and reconfiguration of the failed VWM or        the transceiver portion of the VWM by preventing future use of        the failure affected VWM by a programming change of all other        VWMs disabling wireless communication to that VWM.    -   9. System recovery from transmission path capacity loading        limitations between any two VWMs by the programmed reallocation        of VWM transceivers to form additional or parallel        point-to-point transmission paths to increase transmission        capacity of the specific affected transmission path.

VSI Method for Lithographic Die Size Limitations

The VSI fine grain vertical interconnect enables the fabrication of ICsthat cannot presently be manufactured by stepped optical, UV, EUV orother EM radiation source based lithographic techniques due to thelimited size of the reticle image field. Present UV stepper lithographictools perform a 4× or 5× reduction of the mask field or reticleresulting in an imaged field of less than 30 mm by 30 mm. Therefore, thelargest IC that can be fabricated is less than the size of the reticleimage field, approximately 25×30 mm at present.

The VSI stacking of circuit layers allow the VSI components or ICs tohave a circuit area that is more than the limit imposed by steppedlithographic methods through the stacking of thinned circuit layers ofarbitrary size until the desired amount of circuit integration isachieved. The stacking is done in combination with fine grain verticalinterconnections between all circuit layers providing an interconnectiondensity that is equivalent or higher than that possible in planar ICs.

Another aspect of die size reduction through the VSI invention is thereduction of interconnection lengths versus planar circuitry.Interconnection resistance is inversely proportional to interconnectionlength, and therefore, the reduction of interconnection lengthsresulting from the VSI invention increases the operational frequency ofthe VSI IC versus an equivalent planar IC. Since interconnect delayaccounts for more than 50% of the delay in large planar ICs fabricatedwith processes with geometry feature sizes of less than 120 nm, thesmaller die size of a VSI IC versus an equivalent planar IC is adistinct and novel means of increased IC performance from the VSIinvention. Further, the dissipated power of a planar IC is directlyrelated to the resistance resulting from interconnection length. Thesmaller die size of a VSI IC versus an equivalent planar IC is adistinct and novel means of reduction of IC power dissipation from theVSI invention.

V-Groove Dual Gate VSI Transistor

Another embodiment enabled by the VSI invention is shown in FIG. 12 andis a V-groove dual gate transistor with a non-optically formed gatechannel. The transistor is formed by the epitaxial deposition of a NPNor PNP sequence of semiconductor layers where the channel is lightlydoped and the adjacent layers are heavily doped. The FIG. 12 shows twoanisotropically formed V-groove gates 1201 and 1202 that transect thegate channel layer 1205. Source 1203 and drain 1204 are in contact withthe heavily doped layers 1206 and 1207 respectively. The V-groove gatesare separated by oxide layers 1208, 1209.

The gate channel 1205 can be formed with an arbitrary thickness and canbe formed with a thickness of over 250 nm and less than 10 nm and with athickness of 1 nm; the channel is not formed from an optical process,and therefore, does not suffer from the current restrictions that arewell known when using optical lithography equipment to form transistorfeatures that are less than 100 nm. The forming of the channel layer andits thickness is determined by the capability of epitaxial equipment,which is known to be able to deposit semiconductor layers of 1 nm. Thetransistor or FIG. 12 functions when voltages are applied to one or bothgates 1201 or 1202 which changes the conductive state of the low dopedgate channel 1205 between the V-groove shaped gates 1201 and 1202. Theoperation of the transistor is similar to convention MOS transistors.

The transistor of FIG. 12 is fabricated by first forming a firstV-groove in a first surface of the semiconductor substrate, preferablyformed on a substrate with a barrier layer or buried etch stop layersuch as an SOI substrate. The V-groove formation by anisotropic etchingis well known. A thin layer of dielectric is then formed over the firstV-groove and an electrode is deposited and patterned. The first surfaceis then bonded to a surface of a VSI circuit stack or is held in such amanner that the underlying substrate [not shown] can be removed toexpose the lower device layer 1206 where upon a dielectric layer isdeposited and a second V-groove etched such that the tip of the secondV-groove is adjacent the first V-groove and transects the channel layer1205. A dielectric layer and electrode are then fabricated in theV-groove as with the first V-groove. It is preferable that the length ofgate channel separating the two V-groove tips be made as short aspossible.

If the gate channel layer 1205 is less than 100 nm it is preferable butnot necessary that the tips of the V-groove gates 1201, 1202 passthrough the gate channel layer 1205, the tips need only come within lessthan 20 nm to cause a change in the conductance of the channel. This isdue to the ability of the tip shape to create a sufficient high fieldwhen a voltage is applied. FIG. 13 shows an example of a V-groove dualgate transistor with one or both V-groove gates 1301 and 1302 notintersecting the low doped gate channel 1305. It should be noted that inthis configuration of the V-groove gates 1301, 1302, the source 1308 anddrain 1305 must be on opposite sides of the semiconductor layers toavoid a short circuit condition.

The V-groove transistors of FIG. 12 and FIG. 13 can be operated toreduce source to drain off condition leakage. This is done by operatingboth gates in parallel or by using one of the gates to affect thethreshold switching voltage of the transistor.

Elimination of the Floating Body Effect in PD SOI Circuitry

Partial Depletion [PD] SOI MOS transistors suffer from an electricalphenomenon called the Floating-body effect. The floating-body effect isa condition of excess charging in the transistor [gate] channel and atthe interface of the channel drain regions. This excess charging resultsfrom the impact ionization of hot-carriers in the channel due to highsource to drain electric fields across the channel region. A furtherresult of hot-carrier impact ionization is a rise in the temperature ofthe channel and this is due to the poor thermal conductivity of theburied oxide layer underlying the transistors of the SOI substrate.

FIG. 14 shows a typical SOI MOS transistor in a VSI circuit layer withsource contact 1401, gate 1403, drain contact 1402 and channel region1404 and drain region 1405. The transistor of FIG. 14 is shown in thepreferred embodiment as integrated as part of a circuit layer in a VSIIC and with the substrate removed stopping at the buried oxide layer ofthe SOI substrate. The SOI buried oxide layer may be removed or reducedduring VSI backside processing from its original thickness to a desiredthickness by conventional semiconductor processing means. A dielectric1406 with a higher thermal conductivity than oxide is deposited such asAl₂O₃ [sapphire] or diamond to a desired thickness. Optionally, a metallayer 1407 may be deposited; in the preferred VSI embodiment, a metallayer such as aluminum or copper would be used to serve as a means toform horizontal interconnection structures such as a ground plan, orvertical interconnect and bonding means between VSI circuit layers, inaddition to this aspect of the invention, as a means to conduct asignificant portion of the thermal energy resulting from thefloating-body effect away from the transistor. It is also an aspect ofthe invention that the metal layer 1407 have a capacitive coupling witha portion of the back side of the transistor body such as the channel ordrain region so that bias voltages can be applied to actively offset thechannel charging effects. The proximity of the metal layer 1407 to thebackside of the transistor also acts to assist in the thermaldissipation of the transistor due the higher thermal conductivity ofmetal layer versus that of dielectric 1406.

This invention for the elimination or reduction of the SOI floating-bodyeffect is practiced through the VSI process because the VSI processingsequence provides, as one of its process sequence steps, for thethinning of the back side of an electronic circuit wafer to a buriedetch stop layer. Further, the two novel features of this invention thatenable the elimination or reduction of the SOI PD MOS transistorfloating-body effect are enhanced thermal dissipation of transistorsthrough immediate contact with the back side of the transistor body andthe formation of an electrode in proximity to portions of the backsideof the transistor body in order to apply a voltage bias to reduce thetransistor channel charging. These two novel features of the inventioncan be implemented in combination or separately.

This method of reducing or eliminating the floating-body effect of PDSOI MOS transistors can also be implemented by thinning the SOIsubstrate to the buried oxide layer independently or with the SOIsubstrate first bonded to a holding or carrier substrate. Theimplementation of this method for controlling the floating-body effectof PD SOI MOS transistor is not limited in its use through the VSIinvention, however, it does require the removing of the underlyingsubstrate to the buried oxide layer 1406.

VSI Low Substrate Leakage Transistors

Substrate leakage in MOS transistors results in increased powerrequirements, resulting in increased circuit thermal dissipation, and isa limiting factor in the design and the integration progression of largeICs and their operating performance. The VSI invention enables thefabrication of a low substrate leakage MOS type transistor throughfabrication of a Substrate Leakage Barrier [SLB] under the transistorgate and blocking the substrate leakage path between source and drainregions of the transistor.

FIGS. 15A and 15B show prior art transistor structure. FIG. 15Arepresents a logic transistor fabricated in a bulk CMOS process and FIG.15B represents a logic transistor fabricated in a SOI CMOS process. Thetransistor leakage path 1501 a is shown in FIG. 15A. No such leakagepath exists in FIG. 15B, a Full Depletion [FD] SOI transistor, however,to achieve this result required that the source 1501 b and drain 1502 bof the transistor be raised out of the plane of the gate 1503 b addingto the complexity of fabricating the transistor. The buried oxide layer1504 b of the SOI substrate used in FIG. 15B is shown directly below thetransistor source 1501 b, drain 1502 b and channel 1505 b.

The VSI SLB is formed from the backside of the transistor gate regionafter the substrate is thinned in accordance with the VSI processingsequence, wherein access to the underside of the gate region is hadthrough conventional semiconductor processing. It is the preferredembodiment that the SLB be part of the VSI fabrication processing,however, the fabrication of the SLB is not limited to use with the VSIinvention, but can be implemented on any appropriately thinnedelectronic circuit substrate.

The structure of the SLB 1503 c is shown in cross section in FIG. 15C.It is fabricated from a conventional bulk MOS transistor or a PD SOItransistor once the underlying substrate indicated by dashed line 1506 dhas been removed to within close proximity of the back side of thetransistor body drain 1504 d, channel 1501 d and source 1505 d as shownin FIG. 15D. The controlled thinning of the backside of the substrate toa specific thickness can be accomplished by various means such as grindand polishing, RIE [Reactive Ion Etch] or spray etching with suchsilicon selective etch agents as KOH with spray processing.

The backside formation of the SLB is preferably formed with use of abarrier 1502 d layer under the device layer which acts as a buried etchstop layer during substrate removal processing. Such barrier layers arepresent in a SOI [Silicon on Insulator] substrate; in the case of a SOIsubstrate, the buried oxide layer which is typically several thousand Åsin thickness can be formed in a thickness range of 50 Å to 500 Å, sincethe intended function of the buried oxide layer of the VSI invention isnot isolation but a barrier layer or etch stop to provide a means forwell controlled termination of the removal process of the semiconductorsubstrate; a means to achieve wafer thinning as part of the VSI wafercircuit stacking method. An alternative barrier layer is the formationof an epitaxial layer beneath a device layer. A barrier layer such asGeB [Germanium Boron] with a Boron doping concentration greater than10²⁰ boron atoms/cm³ and a Germanium concentration sufficient to offsetlattice dislocations due to the high concentration of Boron atoms andtypically in a concentration in excess of 25%. The GeB epitaxial layerhas the property of etching 100 to 1,000 times slower than silicon inthe presents of a selective silicon etch agent such as KOH, and enablinga well controlled means to achieving removal of the substrate. Thecapability of uniformly terminating the removal [thinning] process ofthe substrate as part of the VSI method is necessary for the correctoperation of the circuit devices formed in the device layer.

The SLB of the VSI invention is implemented from the backside of aconventional MOS transistor structure of a thinned VSI layer as shown inFIG. 15D, in the preferred embodiment this occurs after formation of thetransistor and bonding of the substrate of the transistor face down suchthat the backside of the substrate of the transistor is a new topsurface of the VSI stack and once thinned. The VSI layer is thinned to aspecific thickness either by a controlled etching process or by use of abarrier layer that acts as an etch stop. Examples of such barrier layersare the buried oxide layer of a SOI wafer, a buried nitride layer madein a similar method as the oxide layer in a SOI wafer or an epitaxiallygrown heavily Boron doped layer [1-2E20/cm³] with Ge doping for crystallattice stress relief. Once thinned to the desired thickness the barrieris removed, if required or appropriate, then a hard mask is depositedsuch as silicon dioxide which is patterned through conventionalsemiconductor lithographic and RIE means to form an opening directlyover and overlapping the channel region 1501 d as shown in FIG. 15D. Thedimensions of this opening are such that the subsequent etch processingstep of the silicon substrate through the opening of the hard mask stopson or slightly into the shoulders of the source 1508 d and the drain1510 d doped regions. The removal of silicon directly below the sourceand drain shoulders eliminates the substrate leakage path under thechannel region 1501 c. The SLB 1503 c of FIG. 15C is then formed bydepositing dielectric material such as an oxide. The etch of thesubstrate below the gate channel region is preferably an anisotropicetch, spray wet etch or an etch by RIE means. The amount of the channelremoved is determined by the design requirements of the transistor andwill vary based on the design of the transistor. The depth of thechannel remaining after the etch processing step is typically 50% orless than the channel length 1509 d.

The VSI SLB transistor shown in FIG. 15C is a MOS transistor of eithernpn or pnp type structure. The transistor shown has a source region 1504c, source contact 1507 c, SLB 1503 c, gate structure 1508 c, gatechannel region 1501 c, drain region 1505 c, drain contact 1509 c andburied oxide layer 1502 c of FIG. 15C. The substrate leakage pathbetween the source 1504 c and drain 1505 c through the substrate regionunder the channel region 1501 c is prevented by the formation of thedielectric comprising the SLB 1503 c.

The SLB structure can also be fabricated as one of the gates of a doublegate transistor or provide the dual function as a block to substrateleakage and as the gate of the transistor. A double-gate MOS transistoris shown in FIG. 15F as disposed on the upper layer of a VSI structuresimilar to the MOS transistor shown in FIG. 15D. The construction ofthis transistor uses a very lightly doped channel 1505 f formed by MBE[Molecular Bean Epitaxy] or equivalent means as described in the priorart which achieves an extremely abrupt transition to the underlyingheavily doped transistor body.

The backside fabrication method of the SLB for the transistor of FIG.15F is shown by FIG. 15E, wherein a source contact 1502 e and draincontact 1504 e are formed in contact with the underlying more heavilydoped transistor body 1507 e gate 1503 e oxide mask 1506 e and opening1501 e in the oxide mask 1506 e. The SLB is formed by a RIE orpreferably an anisotropic etch of transistor body under the lightlydoped channel terminating in the lightly doped channel 1505 e as shownin FIG. 15E. The SLB and back side gate are then formed by formation ofan oxide layer 1510 f and conductive layer 1501 f which are shown inFIG. 15F.

The SLB 1511 f of FIG. 15F is shown to be in combination with conductivelayer 1501 f and dielectric layer 1510 f allowing capacitive coupling tothe conductive layer 1501 f to the transistor body 1507 f. There is nosubstrate leakage path from the source region beneath the source contact1502 f to the drain region under the drain contact 1504 f. Thetransistor operates in a conventional manner by application ofappropriate voltage levels to gates 1501 f and 1503 f in order to causethe channel 1505 f to conduct or not conduct. Either gate of thetransistor 1501 f or 1503 f can also be used as a voltage source forbiasing the threshold voltage of the gate region 1505 f in order toimprove the performance of the transistor. The SLB of this transistorcould also be formed as a dielectric without a gate function. Theoperation of this transistor is novel due to lack of doping profileunder the full length of the gate. The channel region 1505 f is invertedby high fields created by the triangular shaped regions of the source1508 f and drain 1509 f and their close proximity adjacent to thechannel region 1505 f. This use of the SLB reduces the fabricationcomplexity of the gate versus prior art due to the elimination of theneed for self alignment and multiple diffusion implants, while providinghigh performance due to the short channel region 1505 f separationbetween the source region 1508 f and drain region 1509 f which can beless than 25 nm due to the shape of the SLB enabled by anisotropicetching from the backside of the transistor channel region.

FIG. 15G shows a similar transistor to that shown in FIG. 15F withoutthe lower gate 1503 f of FIG. 15F. FIG. 15G shows backside gate contact1506 g, dual source contacts 1501 g, 1502 g and dual drain contacts 1503g, 1504 g, wherein the additional source or drain contacts are enablingfor the purpose of forming horizontal interconnections on either side ofthe VSI device layer; the source and drain contacts are formed withconventional semiconductor fabrication techniques. The SLB structure1507 g takes the form of a gate and is formed by conventional RIE orpreferably anisotropic etching stopping in the lightly doped channel1505 g.

FIG. 16A shows a conventionally formed PD SOI logic transistor withsource contact 1601 a, drain contact 1603 a and gate 1602 a, again asthe upper layer of a VSI device layer stack with the substrate removedto a first barrier layer 1605 a allowing access to the backside of thetransistor. A second barrier layer of oxide or nitride 1604 a, andindicated by a dashed line, has been implanted at a depth equal to thechannel depth of the transistor. The second barrier layer 1604 a is lessthan 4 nm thick and preferably 0.5 to 1 nm in thickness. The purpose ofthe second barrier layer is to act as an etch stop for the etchprocessing necessary to form the SLB 1608 b as shown in FIG. 16B. Thesecond barrier layer is sufficiently thin to be disrupted as a barrierto conduction by dopant implant processing of the source and drainregions 1609 b and 1610 b to have little effect on the conduction of thesource and drain regions. Additionally, the portions of the secondbarrier layer 1604 b in the source and drain regions could be removedthrough etch processing of the source 1609 b and drain 1610 b regionsfrom either side of the second barrier layer 1604 b and then removingthe barrier layer upon which source and drain regions could be replacedwith epitaxy processing. FIG. 17A shows the removed source region 1702 aand drain region 1703 a stopping on the second barrier layer 1704 a andFIG. 17B shows the source region 1702 b and drain region 1703 b replacedby epitaxy processing after the removal of the second barrier layer.

FIG. 16C is similar to the transistor of FIG. 16B but with the SLBformed in the transistor body 1607 c as a gate with conductive layer1608 c and gate dielectric 1606 c resulting in a double gate transistorin combination with gate 1602 c. Additionally, the transistor of FIG.16C is shown with dual source contacts 1601 c, 1609 c and dual draincontacts 1603 c, 1610 c which can be formed with conventionalsemiconductor fabrication techniques.

Another aspect of the low leakage SLB transistor of FIG. 15C is itsembodiment as a 1T low leakage DRAM memory cell in a VSI IC where chargeis held in the transistor body by using appropriate biasing of the dualgates. A significant limitation of all current DRAM memory cells is ahigh rate of charge leakage with increased operating temperature and theinability to reduce memory cell size in keeping with small fabricationgeometries due to limitations in fabricating smaller capacitors. The SLBSOI MOS transistors of FIG. 18A are shown in cross section with a dataline [bit line] of an array of memory cells using the invention. Here aconventional logic gate 1801 a has a shared data line connection 1802 ato transistor body 1804 a and SLB 1803 a formed as part of a capacitorstructure consisting capacitor inner electrode contact 1810 a, capacitorbody 1805 a, capacitor dielectric 1806 a, capacitor outer electrode 1807a and outer capacitor electrode contact 1809 a. The SLB is formed byanisotropic etch of the transistor body under the gate 1801 a andextending across to one adjoining memory cell where upon a severalconventional capacitor fabrication sequences can be used, wherein thecapacitor body 1805 a may be formed as part of a copper electroplatingprocess. It should be noticed that the adjoining transistors 1812 a areseparated by dielectric 1811 a which is shown as a portion of theblanket deposition for the capacitor dielectric. Since the capacitor isformed on the backside of the transistor, it can be fabricated withoutthe need to accommodate layout of the gate line [not shown] and dataline 1801 a interconnection which is a design limitation in stackedcapacitor planar DRAM memory cells. The backside access to either thetransistor channel region 1810 a or drain region 1813 a does so withoutincreasing the size of the memory cell beyond a minimum area representedby the crossing of only the gate line and the data line while alsoallowing the size of the capacitor to be as nearly as large the totallayout area or foot print of the memory cell, and therefore, avoidingthe area limitations present in the fabrication of current planar DRAMmemory cells. Further, this memory cell design or layout enables a cellsize typically of less than 5F² and as small as the practical limitationfor all such 1T memory cells of 4F², where F is the minimum feature sizeused by the lithography system in the fabrication memory cell. Thismemory cell is also novel due to the presents of an outer electrodecapacitor contact 1809 a which enables capacitors of a given gate lineof memory cells to be selectively and independently biased versus thememory cells of other gate lines assisting in the performance of readand write operations of the memory cells. The outer capacitor contact1809 a also allows the capacitor of the memory cell to be calibrated toa predetermined level of charge prior to a write operation, this allowsa common voltage base reference to be used for a gate line memory cellsor portion thereof when multiple data bits of information are stored permemory cell.

FIG. 18B shows a VSI 1T DRAM cell made from a PD SOI transistor. It isknown in the art that the floating body effect of a PD SOI transistorcan be used as a memory cell. The VSI invention allows this type of DRAMmemory cell to be implemented with a backside capacitive coupled contact1801 b preferably formed by anisotropic etching from the exposedbackside of the transistor body and isolating the adjacent transistordrains. The backside contact 1801 b can sever as a voltage bias to drivea calibrated charging of the transistor body, and as a means to sensethe voltage of the charge on the transistor. FIG. 18B shows transistorgate 1802 b, data line 1803 b, channel charge storage node 1804 b 1 ordrain charge storage node 1804 b 2, and dielectric 1805 b. The backsidecontact 1801 b is shown as common to adjacent transistors, but couldalso be formed as separate contacts to each transistor withoutsignificantly affecting the small size of the memory cell which isapproximately equal to 4F², where F is the minimum feature size of theelements of the transistor.

FIG. 19A and FIG. 19B are dual function devices with capability tooperate as a logic transistor or as an EEPROM which is enabled throughuse of a VSI SLB in the form of an EEPROM floating gate. The SLB 1910 acan be fabricated in the form of a floating gate to create the functionof a low leakage EEPROM memory cell from a conventional MOS transistor.The FIG. 19A shows a low leakage logic transistor with SLB 1910 a formedin a similar fashion as in the transistors shown in FIG. 15C and FIG.16C except for the fabrication of a floating gate [FG] 1901 a and aprogramming gate [PG] 1902 a; dielectric isolation of the FG from thetransistor body is not shown. The FG and PG of the SLB structure acts toprevent substrate leakage in the conventional operation of the MOStransistor. The fabrication of the SLB 1903 a is enabled preferably aspart of the VSI process wherein the backside of the transistor of FIG.19A is accessed through conventional semiconductor processing. The dualfunction transistor device of FIG. 19A consists of source contact 1907a, gate 1906 a, drain contact 1908 a channel region 1905 a, FG 1901 aand PG 1902 a. The MOS logic transistor operates in a conventionalmanner when there is no charge, relative to the transistor type beingnpn or pnp, on the FG 1901 a or when there is a biasing charge tocorrect for deficiencies of the operating threshold voltage of the gate1906 a. The MOS logic transistor operates like a EEPROM devices when theFG 1901 a is charged and appropriate voltages applied to the gate 1906a, the gate 1906 a can also be used in the reading of the EEPROM cell byproviding a partial voltage and therefore enabling the FG to carry alower effective operating charge. The charging of the FG 1901 a isaccomplished by the PG 1902 a through capacitive coupling to the FG andis enhanced by the present of the electron emitting edges 1904 a of thePG on the side of the SLB which create electric fields between the PGand FG causing the injection of the electrons into the dielectric 1909 abetween the PG and FG. The FG is erased by reversing the polarity of thecapacitive coupling of the PG 1902 a to the FG 1901 a, this process isenhanced with the electron emitting edges 1903 a on the FG which createelectric fields causing the injection of electrons into the dielectric1909 a between the FG and PG. The transistor gate 1906 a can also beused as a second PG during the writing or erasing of the FG withapplication of an appropriate voltage. The FG is programmedindependently of the programming voltages applied at the source or drainregions of the transistor, which allows the value of the FG to be readcontinuously during programming operations improving the accuracy of theapplied charge to the FG and lowers the time required for programming. Afurther advantage of the FG and PG structure is that the FG is chargedand discharged from the PG greatly reducing or eliminating theopportunity for charge trapping in the dielectric 1909 a which is knownto shorten the useful life of current planar EEPROM devices, and reducesthe leakage of the charge from the FG during operation of the channeldue to the use of lower transistor operating voltages as a result oftransistor geometry scaling. The lower leakage condition of thetransistor and the FG improves the reliability of the EEPROM for use instoring multiple data bits per memory cell. The design of the MOS deviceof FIG. 19A enables the EEPROM memory cell to be scaled to the samegeometries of logic transistors and to achieve a layout area ofapproximately of 4F², where F is the minimum fabrication feature size ofthe device; both of which are improvements over current planar EEPROMmemory cells. It should be noted that the gate structure 1906 b could befabricated as a SLB FG structure similar to the SLB FG structure 1903 ain FIG. 19A making a dual EEPROM gate structure or the FG structure 1910b may be fabricated as conventional gate.

An additional aspect of the dual function devices shown in FIG. 19A andFIG. 19B is to use the gate 1906 a or 1906 b to enable the individualEEPROM by providing a partial reference voltage sufficient to cause theEEPROM channel to conduct if the FG is charged or encoded with a datavalue. This allows the FG to be encoded with data values at lower chargevalues, and it also provides a means for lowering the probability forcross gate line induced noise in EEPROM memory arrays.

It is important to note that a benefit of charging and discharging the aFG 1901 a from a PG 1902 a is to minimize or prevent the accumulation ofcharge in the dielectric separating the FG and PG, and avoiding theopportunity for charge accumulation in the gate dielectric in contactwith the channel which can bring about an unwanted change in theconductance of the channel; this results in extended programming cyclesof the FG and a longer useful life of the EEPROM device. The electronemitter edges 1903 a, 1904 a formed on either side of the EEPROM gate1910 a of the FG and PG create stronger electric fields when programmingvoltages are applied to the PG and since these stronger fields onlyexist when the PG has applied programming voltages and the voltagedifferences between the source and drain of an EEPROM embodiment withelectron emitter edges on the FG and PG of FIG. 19A are not sufficientto effect the programmed charge of the FG during its operation at normalvoltage potentials. Further, the gate dielectric over the channel of theEEPROM does not have to be made thin to support electron injection. Thisprogramming process of the FG reduces the probability that electronleakage between the gate and the source or drain is greatly reduced bythe design of EEPROM gate 1910 a. It is also important to note that as aresult of the lower leakage of the VSI EEPROM memory cells made withwrite and erase functions implemented only through a PG and not throughthe source and or drain regions of the EEPROM device, a calibrated orstandard reference value can be used as a reliable initial memory cellvalue for writing or reading multiple storage values when more that onebit of data is encoded or store on a memory cell. The benefits of theinvention's EEPROM extended write/erase life cycles and low FG chargeleakage also apply to the structure of the V-groove EEPROM gatediscussed herein for the same reasons due to the electron emitter edgespresent in the V-groove gate structures such as the one shown in FIG.19B and FIG. 19C.

The FIG. 19B shows an alternative VSI SLB dual function logic transistorand EEPROM memory cell device with function and capability the same asthe device of FIG. 19A. This device uses a conventionally formed EEPROMFG 1901 b and PG 1902 b gate stack, however, a lightly doped MBE formedchannel 1903 b over a heavily doped transistor body 1904 b is usedrather than conventional source drain diffusion based doping profiles.The PG has contact 1905 b. The transistor function is enabled byanisotropically formed V-grooved shaped gate 1906 b, source contact 1907b with transistor body 1904 b and drain contact 1908 b with transistorbody 1904 b. The gate 1906 b makes contact into the channel region 1903b and creates a leakage barrier between source and drain regions oftransistor body 1904 b. The FG and PG surfaces of dielectric 1909 b areshaped in the manner presented in FIG. 20F to provide electron emitteredges 2001 f through 2004 f to enhance the ability of the PG to chargeand erase the FG. The design of the MOS device of FIG. 19A enables theEEPROM memory cell to be scaled to the same geometries of logictransistors and to achieve a layout area of approximately of 4F², whereF is the minimum fabrication feature size of the device; both of whichare improvements over current planar EEPROM memory cell.

The FIG. 19C and FIG. 19D show double gate EEPROM memory cellembodiments of the VSI SLB invention. The double gate EEPROM provides ameans for lowering the charge storage level per FG required to implementsingle and multiple bit storage capability. The gate channel 1903 dcorresponds to 1903 b of FIG. 19B. In one embodiment, FG 1901 c or 1902c of FIG. 19C, or FG 1901 d or 1902 d of FIG. 19D is given a partialcharge or reference charge and the other gate is encoded with the chargelevel representing the data stored, and therefore, the encoded gaterequires less charge in order to represent a specific data value. Thisis useful because lower FG charges have lower probabilities ofspontaneous charge loss. This same function can also be achieved in thedual function devices shown in FIG. 19A and FIG. 19B where the gate 1906a or 1906 b would provide a dynamic or enabling partial charge bias.

FIG. 19E and cross sections of FIG. 19E-AA and FIG. 19E-BB show a dualfunction logic transistor and EEPROM memory cell device withconventional logic gate 1902 e, 1902 e 1 and EERPOM gate 1911 e 1,wherein the EEPROM gate has FG 1908 e 1 and PG 1909 e 1. The sourcecontacts 1901 e, 1901 e 1, 1905 e 1 and drain contacts 1903 e, 1903 e 1,1907 e 1 contacts can be positioned on either side of the transistorbody as shown with all possible contacts present. The distinction ofthis device is that the EEPROM can be continuously programmed while inoperation. This is accomplished through programming of the FG 1908 e 2through PG contact 1912 e 2 or by optional PG contact 1904 e 2 which areout of the line of the transistor body as shown in FIG. 19E-BB. Theportion of the EEPROM gate of FIG. 19E-BB which is out of the conductivepath of the device body shown in FIG. 19E-AA is enhanced with electronemitter edges 2001 f through 2004 f as shown in FIG. 20F but only overthat portion of the FG and PG that are out of line of the body of thedevice. The unique V-groove shape of the PG 1904 e 2, the tip of whichis positioned in contact with the oxide layer 1910 e 2 directly underthe FG, creates a strong electric field for injection of electrons intothe oxide layer 1910 e 2. The programming of this device can be donewithout changing the conductance of the channel 1906 e 1 allowing thecontinuous monitoring of channel conductance or use of that conductancewherein it can provide a continuous feed back to an analog circuitnetwork as an analog memory device. The logic gate 1911 e 1 providesadditional control of the operation of the EEPROM memory cell such as alower range of voltages on the FG or a enabling switch.

FIG. 20F shows the cross section of a PG, FG and the thermal grown oxidedielectric separating a PG and FG of an EEPROM gate such as the gate1910 b of FIG. 19B. Electron emitter edges 2001 f, 2002 f, 2003 f and2004 f are shown which create electric fields that assist in theinjection of electrons from PG 2005 f in to the oxide 2007 f during awrite or charging operation or from FG 2006 f into the oxide 2007 fduring an erase or discharging operation of the FG. The electron emitteredges enable lower voltages to be applied to the PG in order to chargeor discharge the FG than would be necessary if the surfaces of the PGand FG were parallel surfaces. The electron emitter edges 2001 f through2004 f are fabricated by patterning the oxide of the FG 2006 f. FIG. 20Ashows the cross section of a FG 2002 a and an overlying hard mask 2001 asuch as a nitride film that has been partially patterned exposing aportion of the FG 2003 a. A second lithography step completes thepatterning of the hard mask 2001 b and exposes the other side of the FG2004 b as shown in FIG. 20B. Two lithography steps are required tocreate the hard mask pattern 2001 b because it is assumed that the widthor length of the FG is of a dimension approaching the minimum featuresize of the lithography process, and therefore, could not be imaged inone step. The FG 2003 c is then oxidized creating the well known bird'sbeak oxide shape 2005 c and 2006 c on either side of the hard mask 2001c as shown in FIG. 20C. The hard mask 2001 c is then stripped as shownin FIG. 20D and a second thermal oxidation step creating bird's beakoxide shapes 2001 e and 2002 e, and resulting in the formation ofelectron edges 2003 e and 2004 e. The thickness of the oxide at thispoint can be reduced or increased by etching or additional dielectricdeposition to adjust what will subsequently be a vertical separation ofthe electron emitter edges. The PG 2005 f is then formed over the oxideand in the same step forming the electron emitter edges 2001 f and 2002f. The vertical separation of the electron emitter edges is determinedby the amount of thermal oxide grown. Thermal oxide growth is a wellknown and well controlled process, and therefore, the verticalseparation of the electron emitter edges can be well controlled which inturn is directly related to the predictable and uniform operation of theEEPROM memory cells.

It is important to note that a benefit of charging and discharging the aFG 2006 f from a PG 2005 f is to minimize or prevent the accumulation ofcharge in the dielectric separating the FG and PG, and avoiding theopportunity for charge accumulation in the gate dielectric in contactwith the channel which can bring about an unwanted change in theconductance of the channel; this results in extended programming cyclesof the FG and a longer useful life of the EEPROM device. The electronemitter edges 2001 f, 2002 f, 2003 f, 2004 f of the FG and PG createstronger electric fields when programming voltages are applied to the PGand since these stronger fields only exist when the PG has appliedprogramming voltages and the voltage differences between the source anddrain of an EEPROM embodiment with electron emitter edges on the FG andPG of FIG. 20F are not sufficient to effect the programmed charge of theFG during its operation at normal voltage potentials. Further, the gatedielectric over the channel of the EEPROM does not have to be made thinto support electron injection. This programming process of the FGreduces the probability that electron leakage between the gate and thesource or drain is greatly reduced by the design of EEPROM gate. It isalso important to note that as a result of the lower leakage of the VSIEEPROM memory cells made with write and erase functions implemented onlythrough a PG and not through the source and or drain regions of theEEPROM device, a calibrated or standard reference value can be used asreliable initial memory cell value for writing or reading multiplestorage values when more that one bit of data is encoded or store on amemory cell. The benefits of the invention's EEPROM extended write/eraselife cycles and low FG charge leakage also apply to the structure of theV-groove EEPROM gate discussed herein for the same reasons due to theelectron emitter edges present in the V-groove gate structure of FIG.19B and FIG. 19C.

The transistor and EEPROM structures presented herein have been shownincorporating polysilicon floating gates. This is not a limitation onthose transistors or memory cells shown and the well known art of ONO[Oxide, Nitride, Oxide] used for trapping charge in EEPROM cells orother such charge trapping dielectric film stacks can also be used toinstead of the polysilicon floating gate illustration.

It should be understood that the relative positions of transistor gatestructures and that of an EEPROM gate structure on either side of atransistor body as shown in the various figures does not limit theiruse, and that these structures can be positioned opposite the order ofthat shown.

VSI Quad Gate Low Leakage Transistor Structure and Interconnect

Transistor source drain substrate leakage can be reduced by configuringthe geometry of the gate so that it has more than one surface adjoiningthe transistor gate region. Dual-gate and triple-gate transistors arewell known in the art. The dual-gate and triple-gate transistorstructures have been fabricated with a planar process. The fabricationof a quad-gate transistor is a novel aspect of the VSI invention. It isnot apparent that present planar processing methods can be extended toenable the fabrication of quad-gate transistors.

FIGS. 19F1 through 19F5 show a first preferred VSI method for thefabrication of a vertical transistor with quad gate structure. Thetransistor shown in FIG. 19F5 is a quad-gate transistor implementedthrough VSI fabrication processing methods, which enable both sides ofan integrated circuit to be processed, however, the fabrication of thisquad-gate transistor is not limited to the VSI fabrication processingtechniques. FIG. 19F5 shows a quad-gate transistor with two gate bodyregions 1905 f 5, 1908 f 5, quad-gate dielectric 1913 f 5, gateelectrodes 1906 f 5, 1910 f 5, gate contacts 1901 f 5, source contact1902 f 5, source transistor body region 1904 f 5, 1907 f 5 draintransistor body region 19012 f 5, 1907 f 5, drain contact 1903 f 5 anddielectric layers 1914 f 5, 1909 f 5, 1911 f 5. The gate electrodes 1906f 5, 1910 f 5 surround the transistor body enabling the completeinversion of the transistor gate region when a threshold voltage isapplied. Although the gate electrodes are connected in common causingboth gate regions to invert simultaneously, the quad-gate electrodes1905 g 5, 1913 g 5 could also have been fabricated to operateindependently as shown in FIG. 19G5. FIG. 19F5 clearly shows that thetransistor body is vertical passing through the VSI circuit layer 1909 f5, and therefore, can also provide the additional function of a verticalinterconnection.

The fabrication sequence of the quad-gate transistor of FIG. 19F5 isshown in FIG. 19F1 through FIG. 19F4. FIG. 19F1 shows the fabrication ofthe quad-gate electrodes 1901 f 1 in dielectric layer 1903 f 1 overlyingdielectric layer 1904 f 1 and semiconductor substrate 1905 f 1. Thequad-gate electrode is further overlaid by dielectric layer 1902 f 1.The circuit fabrication shown is accomplished with established ICfabrication processes.

FIG. 19F2 shows a via 1901 f 2 etched through the dielectric layers 1902f 2, 1904 f 2 and quad-gate electrodes 1903 f 2 terminating on thesemiconductor substrate 1906 f 2 with substrate contact 1905 f 2. Thecircuit fabrication shown is accomplished with established ICfabrication processes.

FIG. 19F3 shows quad-gate electrodes 1907 f 3, 1908 f 3, dielectriclayers 1902 f 3, 1904 f 3, 1905 f 3 and semiconductor substrate 1906 f 3with the addition of quad-gate dielectric layer 1901 f 3 over the sidewalls of the via 1901 f 2 shown in FIG. 19F2. The growth or depositionof the quad-gate dielectric 1901 f 3 will cover the semiconductorsubstrate contact 1903 f 3 and is not shown, it is removed by use of RIEprocessing techniques enabling a directional or differential etch of thehorizontal surface of the substrate contact 1903 f 3 versus thequad-gate dielectric 1901 f 3 on the via side wall. This etch processingremoves that portion of the quad-gate dielectric from the substrate 1906f 3 which is required to be open as a crystalline seed surface forsubsequent epitaxial growth of the transistor body.

FIG. 19F4 shows the quad-gate electrodes 1907 f 4, dielectric layers1902 f 4, 1913 f 4, 1911 f 4, semiconductor substrate 1912 f 4 andquad-gate dielectric 1901 f 4 with the addition of the transistor bodysource 1903 f 4, 1906 f 4, gate 1905 f 4, 1908 f 4, and drain 1909 f 4,1906 f 4 regions. The transistor body regions were fabricated byconvention semiconductor epitaxial controlled growth techniques. Theepitaxial grown transistor body is grown from the substrate seed contactarea 1910 f 4 at the bottom of the transistor via. The doping profilesof the source, gate and drain regions are formed during the epitaxialgrowth of the transistor body. The distance from the semiconductorcontact 1910 f 4 to the gate regions 1905 f 4, 1908 f 4 are knowndistances along the transistor body from the semiconductor substrate1912 f 4 and the epitaxial growth rate is used to determine the use ofdoping constitutes and concentrations required to form the variousregions of the transistor body during epitaxial growth of the transistorbody. Once the quad-gate transistors of the VSI layer are completed,overlying horizontal interconnection is formed as needed, and thecircuit layer is then ready for bonding onto a another substrate and theremoval of the underlying substrate 1912 f 4 up to dielectric layer 1911f 4. This followed by backside fabrication of the drain contact 1903 f 5and the fabrication of additional interconnection, as needed.

Additional quad-gate transistors could optionally be formed on thebackside of the completed first quad-gate VSI circuit layer through theuse of a semiconductor substrate with a dielectric barrier layer such asa SOI substrate. If this were desired, the removal or thinning of theSOI substrate would stop on the barrier layer, and the then underlyingdevice layer of the SOI substrate could be used as a crystalline seedcontact for the growth of the next layer of quad-gate transistors byrepeating the fabrication sequence represented by FIGS. 19F1 through19F4. Such backside fabrication of quad-gate transistors also assumesthat a drain contact and interconnection to it was fabricated during topside first quad-gate transistor circuitry fabrication in anticipation ofthe backside quad-gate transistor fabrication.

FIG. 19G1 through FIG. 19G4 show a second VSI method for fabrication ofa vertical transistor with quad gate structure. The transistors shown inFIG. 19G4 and FIG. 19G5 are quad-gate transistors implemented throughVSI processing which enables fabrication access to both sides of anintegrated circuit, however, the fabrication of these quad-gatetransistors are not limited to the VSI fabrication processingtechniques. FIG. 19G5 shows a quad-gate transistor with two gate bodyregions 1907 g 5, 1909 g 5, quad-gate dielectric 1912 g 5, gateelectrodes 1905 g 5, 1913 g 5, gate contacts 1901 g 5, 1903 g 5, sourcecontact 1902 g 5, source transistor body region 1906 g 5, 1908 g 5,drain transistor body region 1908 g 5, 1910 g 5, drain contact 1911 g 5and dielectric layers 19014 g 5, 1904 g 5, 1915 g 5. The gate electrodes1905 g 5, 1913 g 5 surround the transistor body enabling the completeinversion of the transistor gate region when a threshold voltage isapplied. FIG. 19G5 clearly shows that the quad-gate transistor body isvertical passing through the VSI circuit layer 1904 g 5, and therefore,can also provide the additional function of a vertical interconnection.

The fabrication sequence of the quad-gate transistor shown in FIG. 19G5is shown in FIGS. 19G1 through 19G4, or the fabrication sequence also asshown in FIG. 19F1 through FIG. 19F5. FIG. 19G1 shows the fabrication ofthe epitaxially grown layers 1901 g 1, 1902 g 1, 1903 g 1, 1904 g 1 onthe surface of substrate 1907 g 1, dielectric barrier layer 1906 g 1 andsemiconductor device layer 1905 g 1. The epitaxial layers correspond tothe source 1901 g 1, 1903 g 1 and gate 1902 g 1, 1904 g 1 regions of thetransistor body; the preexisting device layer 1905 g 1 corresponds tothe drain region of the transistor body and is assumed to be dopedappropriately or extended by epitaxial processing.

FIG. 19G2 shows the transistor body formed by etching away thesurrounding semiconductor material to the dielectric layer 1907 g 2overlying substrate 1908 g 2 and leaving the transistor body verticallyoriented with hard dielectric etch mask 1901 g 2 overlying source 1902 g2, 1904 g 2, gate 1903 g 2, 1905 g 2 and drain 1904 g 2, 1906 g 2regions.

FIG. 19G3 shows the quad-gate transistor after fabrication of quad-gatedielectric 1910 g 3, gate electrodes 1904 g 3, 1914 g 3, gate contacts1901 g 3, 1903 g 3 and dielectric layers 1911 g 3, 1915 g 3. The gateelectrodes are deposited at a distance from the dielectric layer 1912 g3 that corresponds to gate body regions 1906 f 3, 1908 f 3 of thequad-gate transistor body. The circuit fabrication shown is accomplishedwith established IC fabrication processes.

FIG. 19G4 shows a completed VSI quad-gate transistor with quad-gateelectrodes 1903 g 4, 1912 g 4, gate contacts 1902 g 4, transistor sourceregion 1905 g 4, 1907 g 4, gate regions 1906 g 4, 1908 g 4, drain region1907 g 4, 1909 g 4, quad gate dielectric 1904 g 4 and the substrateremoved with drain contact 1910 g 4 and optionally formed overdielectric layer 1912 g 3 shown in FIG. 19G3. The quad-gate electrodesare connected in common, but also can be fabricated to operateindependently as shown in FIG. 19G5 or in numerous other single ormultiple quad-gate design configurations.

FIG. 19H shows a VSI quad-gate 1T non-destructive read memory cell. Thissingle transistor memory cell is composed of a quad-gate electrode 1905h 1 surrounding the transistor body of source 1903 h 1, gate 1904 h 1and drain 1909 h 1 regions, gate dielectric 1902 h 1, drain chargingelectrode 1911 h 1, source contact 1901 h 1, drain charging electrodecontact 1912 h 1 and dielectric layers 1910 h 1, 1906 h 1, 1907 h 1,1908 h 1, 1913 h 1. The VSI quad-gate 1T memory cell operates by storingcharge in the drain region. The amount of charge in the drain region ofthe quad-gate transistor is determined by the voltage applied to thedrain charging electrode 1911 h 1. The charge stored in the drain region1909 h 1 can be sensed through the drain charging electrode contact 1912h 1 enabling the memory cell to be non-destructively read. The memorycell may require periodic refresh of its stored charge depending on therate of charge leakage that may occur from the drain, however, thequad-gate structure will act to reduce or eliminate charge leakagedepending on the geometry of the transistor body and quality of itsfabrication.

It is a further aspect of the 1T quad-gate memory cell described herein,that more than one quad-gate can be used to reduce charge leakage asshown in FIG. 19F5. It is a further aspect of the 1T quad-gate memorycell described herein, that the memory cell can be integrated withadditional logic functions in the same vertical transistor body of thememory cell through the fabrication of additional gate regions andquad-gate electrodes, and additional source/drain electrodes can beadded along the transistor body. It is a further aspect of the 1Tquad-gate memory cell described herein, that the memory cell can beintegrated as the memory element in PLD logic such as FPGA logic orprogrammable combinatorial logic. It is a further aspect of the 1Tquad-gate memory cell described herein, that the a feed back circuit canbe used to accurately monitor the charge or voltage of the memory cellto adjust the charge without a complete refresh of the charge. It is afurther aspect of the 1T quad-gate memory cell described herein, thatthe memory cell can be used to store multiple levels of charge so thatmore than one bit of information can be stored in the memory cell.

VSI IC Yield Enhancement and Dynamic and Static Configuration

The VSI fine grain vertical interconnect enables novel methods of ICyield enhancement after the fabrication of an IC is completed, for ICswith large surface areas, and for ICs where the yield of even one IC perwafer would be acceptable if such yield were obtainable. The capabilityfor post circuit wafer fabrication integration of a large number of VSIcircuit layers has the advantages of simplified IC integration, improvedperformance, and lower overall IC costs. The yield of such highlyintegrated ICs is not possible without a method for configuration of theIC to avoid various expected physical defects in the circuitry of theIC.

Full or multiple redundancy of complete VSI circuit layers enableshigher net VSI IC yields independent of circuit die size. This method ofVSI IC yield enhancement offers unique net VSI IC circuit yieldadvantages when a specific net circuit yield is an applicationrequirement or even the yield of one IC would be acceptable. Fine grainvertical interconnect implements this method of yield enhancement with asmall number of vertical interconnects sufficient to separately enableand power each redundant circuit layer. An example of yield enhancementwith this aspect of the VSI invention is a circuit layer with anexpected planar IC yield of 80% if made fully redundant in a VSIcomponent would have an effective yield of approximately 96%, similarly,an IC with an expected planar IC yield of 60% if made triply redundantin a VSI component would have an effective yield of approximately 93%.It is important to point out that the cost of packaging often is greaterthan the cost of a planar die being packaged, and in certain circuitapplications packaging costs are several times greater than planar diecost, and therefore, VSI circuit layer redundancy can be cost effectivethrough reduction of packaging costs. Circuit test costs are reduced ina similar manner, wherein the cost of testing one VSI IC is less thanthe cost of testing a number of planar ICs that are equivalent to theVSI IC.

Circuit configuration or reconfiguration control circuitry is located onone or more VSI circuit layers separate from the circuit layers to beconfigured through VSI vertical interconnections. The redundant VSIcircuit layers are connected enabling or disabling configurationcircuitry by as many fine grain vertical VSI interconnections as may berequired to achieve the desired control over the use of these circuitlayers, and may range from 100s to 10,000s or more interconnects. Theconfiguration of a VSI IC or component can be implemented withprogrammable circuitry such as PLD or FPGA circuitry using dynamicmemory means, for example SRAM or Flash devices or static means such asfuse or anti-fuse devices, all presently used programming means inplanar PLD circuits. An example of this type of VSI IC is shown in FIG.5.

This aspect of the VSI invention dramatically impacts computerarchitecture by enabling the integration of heretofore more circuitrythan is presently possible with existing IC technologies and withoutregard to the incompatible characteristics of the disparatesemiconductor processes and technologies that may be used or the yieldof any particular circuit layer. The primary objectives of this aspectof the VSI invention are higher IC performance with lower cost throughreduction of conventional package and testing costs, and performancedelays due to packaging interconnections.

VSI ASIC Manufacturing Inventory Method

The VSI integration and yield enhancement methods when combined withstandardized die sizes, and circuit interfaces, communication protocols,layout and placement of fine grain vertical interconnections enable thefabrication of circuit layers that have a varying range of utilizationfor a broad range of end-user or OEM [Original Equipment Manufacturer]applications. This combination of the VSI IC manufacturing integrationand design methods enables the novel method for integrating completedVSI circuit wafers from an inventory of various circuit wafer designs.This offers two heretofore unavailable IC manufacturing capabilities:

[1] a method for the manufacturing of completed circuit wafers asintegral components or sub-systems prior to subsequent use in multipleapplication circuits that differ by one or more circuit features such asprocessing capacity, storage capacity, design, method of use or intendeduse; and,

[2] a method for inventory control for reuse of fabrication completed ICcircuitry prior to final circuit integration fabrication.

VSI Stacked Wafer Alignment Method

Another aspect of the VSI invention includes methods for achieving highprecision wafer to wafer bonding alignment with tolerances below currentavailable capabilities of ±1 μm physical alignment [4 μm verticalcontact pitch] and as low as approximately ±5 nm physical alignment. Theobjective of achieving greater alignment precision of wafers prior tobonding is to be able to provide a vertical interconnection pitch thatscales with or is compatible with the pitch of the last horizontalinterconnections of a circuit device layer. This is enabled by the useof specific alignment wafer processing steps in combination with the useof established micro-lithographic alignment means conventionally used incurrently available stepper scanner lithography equipment to alignexposure masks to a wafer or substrate.

The alignment accuracy for of the invention is similar to the alignmentaccuracy achieved with established lithography alignment equipment andhas the capability to scale with ever decreasing circuit geometries.This degree of wafer alignment precision also requires that theindividual lithographic images that are printed across the surface of aVSI circuit wafer be placed at placement tolerance relative to eachother that is typically less than 50% of the minimum feature size of thevertical interconnect patterns on the bond surface layer and preferablyless than 25% of such minimum feature sizes. State of the artmicro-lithography equipment are capable of layer to layer alignment ofless than 20 nm., however, such equipment when first stepping across awafer [so called blind step] exhibit center to center placement ofadjacent stepped circuit images of nominally 100 nm or greater.

The wafers or circuit layers or MEMS device layers used in making a VSIIC are composed of rows and columns of circuits or MEMS and each of saidcircuit or MEMS must be fabricated with a circuit placement accuracyrelative to each other such that all vertical interconnections from oneVSI IC layer to the next VSI circuit layer can be aligned properly. Thecumulative placement variance from first to last stepped image in eitherrow or column can currently be as much as 2 μm. It is the objective ofthe VSI substrate alignment method that the placement of die imagesrelative to each other [in x, y & theta] across a wafer not vary by morethan 50% of the minimum feature size of the last imaged layer or bondinglayer. This is to say the center to center placement of any image on thewafer to any other image on the wafer not vary by preferably more than50% of the final substrate bonding alignment budget. This presently isnot done by as part of lithography processing. This is accomplished byuse of the following processing steps:

-   -   1. Printing a first image with alignment marks on substrate [so        called blind step image] wherein the placement of any image        relative to any other image has a center to center placement        variance when added to the substrate bonding alignment tolerance        of less than the final substrate to substrate alignment budget.        The first printed image may be limited to a first set of        alignment marks prior to the printing of the first circuit image        layer using pattern generator equipment or direct write on wafer        equipment such as those presently used for making circuit masks        using E-beam or optical exposure means. The accuracy of the        placement of blind step images on a substrate is presently        controlled by a precision mechanical substrate stage with        current nominal image to image stepping motion control of less        than 50 nm and with a substrate temperature controlled to        approximately 1° C. and often to 0.1° C. This does not provide        sufficient placement accuracy for VSI alignment method        objectives of less than ±250 nm and preferably less than 100 nm        due to insufficient substrate temperature control. If a value of        4 is used as the CTE for a silicon substrate, then at 0.1° C. an        additional 80 nm of placement variance is incorporated into the        mechanical substrate stage placement accuracy for a 200 mm wafer        and more for a 300 mm wafer. The lithography for planar        circuitry does not require a high precision first image        placement alignment control tolerance. A majority of current        lithography stepper and pattern generation equipment have the        capability to adjust exposure image placement with a high        accuracy of less than 1 nm. The VSI alignment method uses this        current image exposure placement adjustment capability in        combination with the measurement from the substrate stage        interferometer [such interferometers have measurement tolerances        of less than 1 nm] and with immediate measurements of the wafer        or substrate surface temperature to an accuracy of less than        0.01° C. and preferably to 0.001° C. or less. The exposure image        adjustment demagnification means is then further compensated by        a first image placement adjustment calculation for exposure        placement that includes the wafer or substrate expansion or        contraction as a function of its CTE. The temperature        measurement of the wafer or substrate can be either an average        physical temperature measurement calculated from one or more        physical measurements of the top or backside of the wafer or        substrate, or preferably, a distribution of physical temperature        measurements taken over either the front or back surfaces and        wherein the physical position of the temperature measurement is        used as part of the image demagnification and placement        adjustment calculation. The image placement calculation methods        are derived from established physical methods. The blind step or        first on wafer step image exposure demagnification and placement        compensation for all initial image exposures is a combination of        interferometer measurement and substrate temperature measurement        as a function of substrate CTE will enable an image placement        accuracy of less than 10 nm and typically less than 5 nm. The        use of substrate temperature measurement to increase image        placement accuracy also allows the temperature control of the        substrate to be less demanding than current lithography        temperature control methods.    -   2. Printing the wafer bond layer [last imaged layer] aligned to        alignment marks of a lower layer and preferably the marks used        to align the first image layer. This may require that all or        nearly all image layers be aligned to the alignment marks on a        lower layer or preferably the first imaged layer.    -   3. Through substrate interferometer or AFM [Atomic Force        Microscope] alignment as explained below.

The true placement of all first images on a wafer or substrate areprimarily affected by mechanical wafer or substrate stage motion errorand relative expansion or contraction of the wafer of substrate due toit temperature; there are other placement error factors but there areexisting methods for minimizing these placement error factors. The VSIfirst on wafer or substrate imaging alignment budget for all firstprinted images is composed of two components: an image placementadjustment by the image exposure means of the lithography tool of themechanical substrate stage position based on the true stage positionmeasurement from the stage interferometer; and, an image placementadjustment by the image exposure means of the lithography tool based onimmediate or in situ temperature measurements of the wafer or substratesurface wherein additional image placement adjustment is calculated fromthese temperature measurements using the CTE for the wafer or substratematerial. This VSI first on wafer or substrate lithographic imagingmethod enables all printed images to have a relative placement alignmentbudget to all other printed images of less than 10 nm and or 5 nm. Thisimage placement alignment budget is a result of the capability ofcurrent lithographic imaging means to make image placement adjustmentsto an accuracy of less than 1 nm from stage interferometer positionmeasurements and substrate surface temperature measurements. The VSIfirst on wafer or substrate image alignment budget objective is an imageto image alignment of all images printed on the substrate relative toeach other all such placements being relative to or initialized from theplacement of the first image on the wafer or substrate; it is understoodthat the initial printed image on the wafer or substrate is printed bythose means presently available and that the placement of all otherfirst on wafer or substrate images are relative to the initial printedimage.

The VSI invention stacked wafer to wafer alignment process is acombination of the alignment accuracy of the image placement of the lastor top printed image on the wafer of substrate and the VSI means foraligning the wafer or substrate images on the bonding surfaces on wafersor substrates to be bonded. The on wafer or substrate image placementsusing the VSI image placement method described herein enables an imageplacement alignment budget of less than 50 nm and or less than 10 nm.The VSI wafer to wafer or substrate to substrate alignment meansdescribed herein enables a alignment budget of less than 50 nm and orless than 10 nm. The combination of these two alignment budgets enablesa final alignment budget for all images on a wafer or substratecorresponding to images on a second wafer or substrate to be less than100 nm and or less than 20 nm. This final alignment budget enables waferor substrates that are to be bonded to be aligned with an accuracy thatis compatible with the pitch of the last metallization horizontalinterconnection layer of a circuit layer presently in the nominal rangeof 0.5 μm to 2 μm.

FIG. 21A and FIG. 21B show an embodiment of the VSI invention stackedwafer to wafer alignment process. This embodiment is accomplished byeither pre-thinning the semiconductor substrate portion 2103 a of acircuit wafer to be bonded to a thickness of less than 25 nm andpreferably less than 10 μm as shown in FIG. 21A, or by etching a minimumof two openings, only one shown as 2100 b, in the backside of thesemiconductor portion of a circuit wafer to be bonded such that at thebottom of the etched openings less than 10 μm of the semiconductorportion of the circuit wafer remains, as shown in FIG. 21B, or acombination of both subsequent substrate thinning and etch of openings.The remaining semiconductor portion of the circuit wafer to be bondedwhen thinned to less than 25 μm and preferably less than 10 μm issufficiently transparent to view conventional alignment marks formed onthe bonding surfaces of the wafers being bonded. Once the backside waferthinning is done or openings are made, wafer to wafer alignment can bedone by established means as those used conventionally in lithographywafer processing tools for alignment of a mask and a circuit wafer beingfabricated, FIG. 21D shows an example of a split field optics alignmentmethod used to align a VSI circuit wafer to a VSI circuit wafer stack.

In all embodiments of this invention, the upper alignment marks 2101 a,2101 b are suspended on or in a layer of transparent dielectric whichallows the clear and unobstructed viewing of all upper and loweralignment marks. In the circumstance where a thin layer of semiconductorsubstrate remains before the dielectric layer, it is thin enough to betransparent. A wafer silicon semiconductor material when thinned to 10μm or less becomes transparent.

The alignment of VSI substrates is similar in method to contact printingmethods. The VSI substrates are brought in contact and alignmentverification is performed. However, wherein contact printing the contactthe mask and substrate must be separated again if additional alignmentadjustments are required, this is not the case with VSI alignment. TheVSI substrates during alignment adjustment can remain in contact due tolow surface to surface frictional forces because their surfaces aresmooth and free of adhesives agents such as photo-resist as in the caseof contact printing, and under little or no pressure load for bring thesurfaces into contact. This enables the alignment of the substrates tobe held in place since no additional motion of the substrates isnecessary once their alignment is completed. Once alignment of the incontact substrates 2103 a, 2104 a or 2103 b, 2105 b is completed, thepressure load on the substrates is increased holding their placement toprevent subsequent loss of alignment due to mechanical vibration due tothe substrate bond processing.

The preferred embodiment of this wafer to wafer alignment invention foraligning a circuit wafer to a circuit wafer stack is by opening two ormore openings in the back side of the wafer stack to expose thealignment marks formed on the backside of the of the last bonded circuitwafer as shown in FIG. 21C. The backside alignment openings 2105 c ofthe wafer stack are extended through VSI circuit layers 2106 c byconventional etching methods down to the alignment marks 2102 c printedon a dielectric layer deposited on the backside of the last thinnedwafer bonded to the wafer stack 2107 c. The extension of the backsideopening 2105 c of the wafer stack removes the previous alignment markused to align the most recent bonded circuit layer to the circuit layerstack 2106 c (this most recent aligned and bonded circuit wafer is nowthe last circuit wafer on the wafer stack 2107, its has an alignmentmark which will be used for alignment of the next circuit wafer to bebonded), the dielectric layers supporting the previous alignment mark2102 c and any remaining semiconductor substrate, then stopping on thedeposited dielectric layers on the bonded side of the circuit wafer mostrecently bonded to the wafer stack.

An alternative alignment method to the alignment embodiments of FIG. 21Athrough 21D is to use a mechanical atomic force microscope [AFM] or suchsimilar measurement tool as are presently in common use for imagingsurfaces on an Angstrom or nanometer scale. This type of alignment couldoptionally follow an initial gross optical alignment of the two circuitlayers to be aligned. The probe 2203 b as shown in FIG. 22B, and theprobe's position corresponding to the cross-section line BB of FIG. 22A,reaches through a backside opening 2208 b of the circuit stack substrate2205 b and through alignment mark openings 2201 a, 2202 a, 2203 a, 2204a and images the overlap displacement or position of the alignment crossmark 2201 b of the top circuit layer of the circuit stack 2210 b and thealignment cross mark 2202 b of the circuit layer 2206 b to be bonded byreaching through openings 2204 b, 2209 b on either side of the alignmentcross marks 2201 b, 2202 b. The type of alignment marks are not limitedto cross alignment marks, the use of cross alignment marks is only forthe purpose of illustration.

The AFM probe simultaneously images the physical positions of thealignment marks 2202 b on the wafer or substrate 2206 b to be bonded andthe alignment cross marks 2201 b of the top circuit layer of a VSIcircuit stack 2205 b onto which the wafer or substrate 2206 b is to bebonded with respect to each other. Once this measurement is made, acalculation is made from this measurement by which the relative positionof the two wafers or substrates 2205 b, 2206 b, is changed, if needed,to bring the alignment marks into alignment, and therefore, wafers orsubstrates to be bonded. The alignment measurement procedure maysubsequently be repeated, as needed, until the desired alignmentaccuracy is achieved.

This alignment procedure requires additional process steps to allowaccess to the bottom wafer alignment marks 2201 b so that they can beimaged by the atomic level probe 2203 b. This step is the selectiveetching by conventional means such as RIE of the dielectric on which themetal pattern that is the alignment mark was formed. It is assumed thatthe layout of the alignment mark is so designed that once the dielectricaround the alignment mark is removed it has sufficient support to remainsuspended in the alignment opening 2208 b which is part of the of thetop circuit layer 2210 b on the wafer or substrate 2205 b, as shown forexample by the suspended alignment mark 2201 b in FIG. 22B. The processof simultaneously imaging both alignment marks with the atomic levelprobe provides measurement data on the relative position of onealignment mark to the other; this imaging of alignment marks ispreferably done at two locations of the wafers or substrates to bebonded in order to measure angular displacement, and is a processsimilar to that used in split filed optical alignment methods. Typicallyonly one of the wafers or substrates is then moved in x, y and angulardirections in accordance with the measured differences between therespective alignment marks. This alignment procedure takes only a fewseconds or less when automated and can be repeated to verify that thedesired alignment has been achieved. The capability of this alignmentprocedure enables wafers to be aligned to an accuracy approaching theresolution of the measurement probe; the probes available today are ableto achieve resolutions of less than 2 nm, and therefore, wafer to waferalignment mark positioning accuracies of less than ±5 nm can be achievedafter assuming an allowance for alignment mark edge roughness nominallyof less than 5 nm resulting from present pattern processing methods.

An another alternative alignment method to the above preferred alignmentembodiments is to use electro-magnetic proximity sensing through a wirecoil pattern. This method of alignment is consistent with the inventionprovided in applicant's U.S. Pat. No. 5,354,695 42:39-44:9 with FIG. 28Aand FIG. 28B, and is included by reference. One coil is a closed looppattern in the position of the alignment mark on the wafer to be bondedand a second and a third open loop coil is in the opening of the bottomwafer again in the position of the alignment mark. Two probes are usedto make contact with one of the open loop coils for propagating a signalthrough the coil which induces a signal in the closed loop coil of thewafer to be bonded. Two probes are used to make contact to the otheropen loop coil as a means to sense the signal induced in the closed loopcoil. The strength of the sense signal is maximized by adjusting theposition of either the closed loop coil or the open loop coils. As partof the fabrication of these coils they are approximately 2,500 Å belowthe surface of the dielectric film they are part of or embedded; this isdone to prevent shorting of the coils during the alignment process andprovides an approximate measure of the separation distance between theclosed and open loop coils. Alternately one open loop coil may be used,in this case there is an electrical load induced on the signal of theopen loop coil by the closed loop coil; this method requires a greaterdegree of signal processing to determine when the desired alignment isachieved.

VSI Method for the Reduction of Distributed Circuitry

The VSI component vertical circuit structure enables a novel designmethod for the reduction of the distributed circuitry of a planarcircuit design or layout. An example of this are sense amps in a memoryarray. Sense amps are distributed through out a planar circuit layout asa result of the electrical necessity to be physically close to a memorybit [data] line in order to determine its state. This distribution ofsense amps is not necessary for the memory array circuit layers of a VSIIC because the sense amps can be placed on a separate circuit layer andshared among multiple memory bit lines on separate circuit layers indirect close coupling [through fine grain vertical interconnections]without addition of significant wiring length between a sense amp andassociated memory bit lines. A second example are the signal repeatersnecessary to propagate a signal over a long distance across a circuit,such as is the case in PLD circuits. The VSI IC fine grain verticalinterconnection lengths of nominally less than 200 μm eliminate the needfor all or most of such repeater circuits over the planar circuit layerwhen used with a smaller die size.

VSI ATE System on Wafer Processing Method

Another embodiment or aspect of the VSI invention is its use in thefabrication of a full on-wafer or substrate ATE [Automatic TestEquipment] system. The objective of the VSI ATE system is to provide thecapability to test all circuits on a wafer or substrate at their maximumpossible speed, to test such circuits during a burn-in procedure, toprogram such circuits based on test data for the purpose ofconfiguration of the circuit due to circuit defects and to program suchcircuits with data for their subsequent application use.

FIG. 23A shows in cross section a VSI ATE system 2301 a. The VSI ATEsystem is a wafer or substrate stack 2302 a composed of circuit layersor groups of circuit layers that provide the pin electronics 2305 a,programmable tester logic and external communication circuitry 2304 a,yield enhancement testing and reconfiguration logic 2306 a and testermemory 2303 a for circuit test vectors. Optional support substrate 2309a may be used as means for handling and or connecting to the VSI ATEsystem; such optional support substrate being made from such flexiblematerials as polysilicon or graphite with a thickness of less than 4 mmand preferably less than 500 μm. FIG. 23A also shows DUT [Device UnderTest] contact means 2307 a as part of the bottom circuit layer 2308 a ofthe VSI ATE system 2302 a. These contact means are fabricated inaccordance with inventor's U.S. Pat. Nos. 5,323,035 and 5,4543,404 andincluded herein by reference. The various circuit layers or groups ofcircuit layers are intended to be modular in design such that dependingon the type of DUT pin or programmable tester logic layers of generic orspecific design required for the DUT circuit type, such logic layers canbe inserted into the VSI ATE system wafer stack, or further, the amountof memory required for the test of a specific DUT type can be varied tomeet the testing requirements.

The VSI ATE system incorporates yield enhancement circuitry 2306 a whichallows the defective pin or tester circuitry to be replaced by sparecircuitry or not to be used. The VSI ATE system yield enhancementcircuitry is implemented from circuitry such as FPGA or fuse circuitrywhich allows dynamic or static implementation of the interconnectionrouting of various circuit blocks of the VSI ATE system electronics. Themajority of the circuitry of a VSI ATE system is devoted to circuitryreferred to in the ATE industry as pin electronics 2305 a. With each DUTIC on the surface of a circuit wafer or substrate there is some numberof I/O contact pads or pins on that IC to be tested and pin electronicsof the VSI ATE system are provided for all or some number of an ICcontact pads. The pin electronics do not take significant circuit areaand since the pin electronics are in immediate physical location to thepads of the DUT there is little or no requirement for additional driveand timing circuitry to be associated with the pin electronics furtherreducing the power required for the pin electronics. The VSI ATE systemin its preferred embodiment simultaneously tests a plurality of ICs orDUTs on a wafer or substrate while in contact with all or the majorityof ICs to be tested. The method and rate of in which the VSI ATE systemperforms DUT testing is a manner of how it is programmed to operate. AVSI ATE system can also be designed to test by contacting only a limitedportion of ICs on a wafer or substrate at one time whereupon such a VSIATE system would be stepped over the surface of the DUT wafer to makecontact with all the ICs to be tested.

The benefit of the VSI ATE system is at-speed IC testing and burn-in ofICs, while the ICs are in substrate form or prior to their separationfrom the wafer or substrate upon which they where fabricated, and earlyIC process yield knowledge. Current ATE systems are large programmableelectronic assemblies of PCBs and because of their size do not presentlyhave the capability to propagate test signals at a level of performanceto test most ICs at their full rated speed while on wafer or substrate.Secondly, present ATE systems are expensive and have the ability to testone or a limited number of IC on a wafer simultaneously. The VSI ATEsystem may be fabricated with as few as 4 circuit layers or more than 32circuit layers with a cost that is approximately less than 25% of thecurrent IC testing costs. A further benefit of the VSI ATE system isthat it enables testing ICs with large numbers of I/Os with contactpitch of 10 μm or less without an increase in cost, since the probepoint contact means 2307 a of the VSI ATE system are lithographicallyformed and programming of interconnections of the pin electronics can berouted dynamically from one IC to another should the ICs of a substraterequire more pin electronics than are available to meet the requirementfor testing all ICs simultaneously.

The input and output of data to the VSI ATE system is accomplished bymaking electrical or optical contact to the VSI ATE system wafer orsubstrate stack or by wireless or radio means or a combination. The VSIATE system may be bonded to a support substrate for the purpose ofmechanical manipulation and or a means through which electrical contactscan be made to the VSI ATE system wafer stack. FIG. 23B shows in crosssection a VSI ATE system 2301 b bonded to a flexible supportingsubstrate 2302 b preferably made from polysilicon or graphite materialand with a thickness of less than 4 mm and preferably less than 500 μm[0.5 mm]. The support substrate 2302 b may optionally make externalelectrical contact to the VSI ATE system 2301 b bring those contacts tothe edge of the support substrate 2303 b. The support substrate 2302 bmay optionally be used to mount fiber optical connections 2304 b, 2305b, 2306 b allowing optical signals to pass through the support substrateeither to optical wave guides or directly to optical transmissiontransceivers on one or more of the circuit layers of the VSI ATE system2301 b. Programming and data for the VSI ATE system 2301 b may be alsobe transmitted or received by optical fiber connections, wired orwireless means.

The FIG. 23C shows in cross section a flexible support substrate madefrom materials like those of FIG. 23B with an open internal area 2304 cwherein the VSI ATE system 2301 c is exposed and is bonded only at itsedges to the supporting substrate 2302 c. Electrical contacts 2303 c maybe fabricated on the support substrate that brings contacts from the VSIATE system 2301 c to the edge of the support substrate 2302 c. Thesupport substrate 2302 c may optionally be used to mount optical fiberconnections 2305 c, 2306 c near the inner edge of the support substrateallowing optical signals to pass through the support substrate to eitherto optical wave guides or directly to optical transmission transceiverson one or more of the circuit layers of the VSI ATE system 2301 c.

The VSI ATE system is intended for use by equipment means in accordancewith inventor's U.S. Pat. No. 6,288,561 and included herein byreference, but is not limited in use to such equipment means.Programming and test data for the VSI ATE system 2301 a, 2301 b, 2301 cmay be transmitted or received by electronic, optical fiber connectionsor wireless means.

VSI Dynamic Memory Reconfiguration and Self Test

Another embodiment or aspect of the VSI invention is its use as astacked memory that has the capability of self test and reconfigurationas a means of recovering from logic and memory circuit defects, andfurther, the integration as desired in combination with the otherembodiments or aspects of the VSI invention presented herein. The yieldand utility of a VSI IC memory is enhanced by the capability tointernally self test and reconfigure the internal physical access tovarious portions of its memory cells and thereby maintain the externalappearance of a continuous memory address space and the continuedutility or availability of the remaining correctly working memory cellsof the VSI IC. This embodiment of the VSI invention is in accordancewith inventor's U.S. Pat. No. 6,551,857 and application Ser. Nos.10/222,816 and 10/143,200, and are herein included by reference.

The primary objectives of this invention versus the current state of theart electronic memories is the reduction of the cost of electronicmemory on a per bit basis through increased yield, increased serial andparallel memory access performance, increased operational utility, andincreased reliability enabled by internal failure detection and failurerecovery reconfiguration circuitry. The objective of dynamic ortransparent failure tolerant operation can also be further enhanced bythe invention through use of its internal failure detection circuitryand programming of the invention's controller circuitry to operate withmultiple copies of stored data. Failure recovery may be also assisted byexternal controlling means upon a request for intervention by theinvention's controller circuitry. A further objective is the making ofhigh density memory systems with a net successful operating circuityield probability in excess of 95% and in excess of 99%, therefore,enabling the option for vertical integration with other technologies ofa near arbitrary range of electronic and optical circuits and MEMS asshown in FIG. 3 without significant reduction in the overall yield ofsuch circuitry.

This type of memory IC accepts a logical address from a data processingIC such as a microprocessor, a graphics processor, the memory controllerof another memory circuit, or a database processor as examples. Theaddress is called a logical address because it is subsequentlytranslated or mapped into a physical address by the VSI IC memoryinvention in the process of accessing the memory location represented bythe logical address. The logical address is an external address used bya data processing IC to access a memory location within the inventionover some known available range of logical addresses recognized by aspecific incarnation of the invention. The use of logical addressing byexternal circuitry enables the addresses used by the external circuitryto appear contiguous over some range when the internal storage over thelogical address range may not be contiguous, and the ability tosimultaneously operate multiple addressing ranges and overlappingaddressing ranges on a as needed or on demand basis through an externalcontrolling means.

Additional primary objectives of the invention are to determine whatquantity of memory storage it has that correctly operates and can makeavailable for external use even in the presents of some number of memorycell failures, and accept an arbitrary logical address range assignmentfor that quantity of memory storage from an external IC or by internalpre-assignment. This external address operating range is also referredto as an address window and there may be more than one address windowthat the invention can be programmed to recognize. The use of multiplewindows may be used to provide simultaneous access in a multiple portmemory circuit or as a means to carry on parallel operations interior tothe memory circuit. As a result of these primary objectives of theinvention, the individual storage capacity of each of the various ICincarnations of the invention may vary and over the useful life of suchICs the storage capacity may change. This is a very valuable capabilityof the invention, because the failure of a small percentage of memorycells does not result in the scrapping of the IC, and perhaps of evengreater value, as memory cell failures occur during the useful life ofan IC of the invention, such failure can be transparent to its use andnot result in its replacement where the cost to perform such areplacement can easily be far greater than the original cost of the ICof the invention.

The primary objectives of the invention are enabled by the use ofinternal self test, error detection, programmable logic and memory faultdescriptors. An embodiment of the invention as a planar circuit is shownin FIG. 24A and for the purpose of this discussion is presented as aDRAM type memory consisting of a memory array 2401 a, and the remainingcircuitry logic consisting of a controller, Error Correcting Circuitry[ECC], Sense Amplifiers, programmable logic router, Cache, addressselect circuitry and memory cell fault descriptor storage. An example ofa block layout of the VSI IC is shown in FIG. 24B, wherein each blocksuch as 2402 b, 2403 b, 2404 b are able to perform memory operationsindependently of each other. However, a memory array block is notlimited to DRAM type cells, but could include any type of memory thatcould be integrated onto planar IC such as ROM, EEPROM, magnetic orSRAM. The memory array is composed of gate lines and data lines whichare placed in an orthogonal orientation with respect to each other andat the respective crossings of the gate lines and data line are locatedmemory cells of the array as shown by the memory array 2410 a of FIG.24A.

The failure recovery capability of the invention enables the yield forits circuitry to be defined as a net successful operating circuit yieldas opposed to the conventional definition used for circuit yield ofdefect free. The invention enables the amount of physical storage of thecircuit to be several times greater than conventional memory circuitryfor equivalent fabrication technology by use of a plurality of memorylayers and such storage cell capacity enhancements as multi-levelstorage. It is due to this large storage capacity capability of theinvention and its novel controller circuitry that circuit yield isredefined in terms of net successful operation per available memorystorage capacity.

The circuitry of the VSI configurable memory invention is shown in FIG.24A in a planar circuit layout with only one memory array 2401 a andassociated control and processing logic. The preferred embodiment of theVSI configurable memory system or subsystem is shown in FIG. 24B as aVSI IC circuit layer stack, diced from a wafer stack, consisting of oneor more logic or controller layers 2401 b used in implementing thememory circuit and one or more memory layers such as 2402 b, 2403 b,2404 b. One or more other data processing layers may also be present asrepresented as 2405 b and may appear at either end of the memory circuitstack as required by a given overall circuit design. Further, 2405 acould also be a layer of additional memory controller circuitry such asredundant circuitry of the controller. The preferred VSI embodiment ofthe invention is to organize the memory circuit layers into a pluralityof memory blocks 2401 c, 2402 c as shown in FIG. 24C, which becomemultiple stacks internal to the VSI configurable memory IC andpreferably each memory stack would have control circuitry on one or morecircuit layers that would allow each such memory stack to have thecapability of independent operation with respect to other memory stacksor blocks, and thereby, its own effective memory circuit yield. Thisstructure of independently operating memory blocks 2401 c, 2402 cincreases the expected total circuit yield by localizing the effect ofmajor circuit defects where the loss of a complete memory stackassociated with memory block 2401 c does not cause the loss of thecomplete VSI IC and would allow the option for use the VSI IC with adiminished capacity.

The invention consists of one or more and preferably a plurality ofmemory circuit layers 2402 b, 2403 b, 2404 b as shown in FIG. 24Bstacked vertically with respect to one or more layers of non-memorycircuitry 2401 b, 2405 b except where such non-memory circuitry isexpressly placed on a memory circuit layer; examples of non-memoryinclude more than logic circuitry such as optical transmissioncircuitry, sensor devices or MEMS devices. Although the invention can beimplemented as a planar IC, the preferred embodiment is as a stacked ICand preferably consistent with the VSI stacking processes. There areseveral advantages to implementing the invention as a stacked memory ICwhich relate to higher performance and lower cost. The principaladvantages are segregation of logic and memory fabrication processes toseparate layers, shared utilization of several memory layers to one ortwo logic layers, design control over die size to achieve a smaller diesize, and at the same time, a nearly arbitrary IC memory density.

The operation of the invention consists of accessing memory layers asmemory read or write operations. Before the memory can be operated thecontroller logic performs an internal test of the memory storage cellsto determine which are defective if any. In the process of performingthe internal memory test the programmable logic is used to configure thememory so that defective memory storage cells are either not used ortheir use is avoided during memory accessing operations. Memory defectsconsist of single defective memory cells, up to one or more defectivegate lines or data lines. During the operation of the memory a portionof the test circuitry, such as the Error Correcting Code [ECC]circuitry, is used to verify that a failure does not occur, and if itdoes, an attempt is made to dynamically correct for the failure ifpossible. It is a primary objective of the invention to provide variouslevels of error free operation, which is based on the intended use ofthe memory. The invention may be configured from a range of operatingcapabilities, from reporting the occurrence of an error, to correctingcertain classes of error as with ECC circuitry, to the use of completelyredundant multiple memory windows whereby memory operations areduplicated in all windows using a combination of error detection anddata comparison mechanisms to guarantee a state of error free operationwhich is referred to as Fault Tolerant.

The testing process of the invention consists of at a minimum of writingand reading bit patterns to memory storage locations and verifying thatthe written pattern is the same as the read pattern over some extendedperiod of operation. When a memory IC is first fabricated, it goesthrough a circuit verification step generally referred to as burn-in.Burn-in is a lengthy process during which an effort is made to determinethe maximum operating speed of the IC and if there are memory cellfailures that are intermittent or a result of extended operation. Theresult of the burn-in process is information, which is used to determinethe maximum operating speed of the memory IC by using various clockingrates that may be generated either within or externally to the IC andthe maximum available useable memory of the IC. A circuit of theinvention will be scrapped should the number of internal memory celldefects exceed a predetermined number. It is a unique attribute of theinvention that a memory IC can have a range of memory capacity whereaspresently memory ICs are scrapped should there be a capacity variancefrom a fixed capacity requirement of present memory ICs.

The preferred embodiment for reconfiguration processing of the inventionuses a programmable gate line router on each memory layer, oneprogrammable data line router located on a controller or logic layer,test and error correcting circuitry, spare programmable gate lineselector circuits, spare gate lines and spare data lines. Associativeaddress circuits may also be part of the reconfiguration circuitry as ameans to add capacity to the gate line or data line reconfigurationcircuitry, this circuitry will preferably use a write once typeprogrammable logic means.

There is gate line select circuitry used in common for all gate lines onall memory layers which is located on a logic layer and is used for theselection of gate lines on the various memory layers. The gate lineselector may be made from circuitry that is programmable multiple times,one time programmable or have a fixed address recognition value, sincethe value of a gate line selector is not likely to change from aninitial assignment. There are a number of spare gate line selectorcircuits that can be programmed to replace a defective gate lineselector circuit which is programmed to select a specific gate line. Theuse of a common gate line selection circuit versus one for each memorylayer conserves significant circuit area. The gate line selector circuitcouples to vertical interconnections to the various memory layers.

A programmable gate line router on each memory layer 2404 d, as shown inFIG. 24D, provides the necessary reconfiguration capacity to interface acommon set of gate line selectors 2402 d and reconfigurableinterconnections 2401 d to a plurality of sets of gate lines 2403 d oneeach on a memory layer. The gate line router is programmable logic suchas that commonly used in a PLD [Programmable Logic Device] andpreferably uses a program once technology such as a fuse technology inorder to route new connections or reconfigure connections permanentlypreventing the use defective gate lines or defective gate line selectioncircuitry. This programmable router is programmed by the controller as adefect is found either during manufacturing [burn-in testing] or duringperiod test verifications over its useful life. Since the expectednumbers of such defects are few, the reconfiguration capacity of thisgate line router or the number of gate lines that it can separatelyroute is also limited based on the expectation of the number of defects,and therefore, is physically small in area. If the capacity of a givengate line router is exhausted by the number of defects, then a reducedmemory storage capacity may result such as eliminating the use of thememory layer, or the use of an associative address circuit routesaddress requests for only defective gate lines of the memory layer to aspare gate line of the memory layer or an alternative memory layer. Theassociative address circuit is not shown, but would be located as partof the controller logic.

The data line programmable router 2404 e shown in FIG. 24E, is part ofthe controller logic circuitry, also uses PLD type circuitry, configuresthe routing of data from data lines when coupled to the memory cells ofa selected gate line. The data line router is reconfigured during everymemory cycle by reconfiguration directives that cause data lines coupledto defective memory cells to be rerouted to spare or defect free datalines; this is done by setting dynamic switches 2405 e or couplingcircuits at various crossing points of the defective data line 2406 e,router line 2403 e, and spare data line 2407 e as shown in FIG. 24E. Ifthe memory block used more than one vertical access bus for all of thecircuit layers, then two reconfiguration router circuits 2401 e, 2402 ewould be required in order to have simultaneous memory access cycles inthe memory block. The data line router is configured during each memorycycle because the defects are defined on the basis of a memory accesscycle, which is per selected gate line and per selected memory layer.The data line reconfiguration directives are created during the burn-inprocess, maintenance of the memory such as part of the system startupsequence or as part of a system directed maintenance, or part of aoperational memory access cycle. These reconfiguration directives arestored in associative address circuits that are typically write onceprogrammable logic. When a gate line on a specific memory layer isselected, all reconfiguration directives for that gate line are readcausing the data line router to be configured specific to the defects ofthe selected gate line and data lines of the selected memory layer. Thedata line reconfiguration directives at least are specific for thereplacement routing of a data line when coupled to single defectivememory cell of a specific gate line, or in the case of a defective dataline where one directive causes all memory cells that would couple to aspecific data line to be replaced by routing to a spare data line.

The cache is part of a logic layer and acts as an associative memorybuffer and referenced by logical addresses. The cache has the capacityto retain the data from one or more selected gate lines from each memorylayer. The cache is organized for some number or depth of selected gatelines by the number data lines of the array, and by a secondorganization by depth and some word length, which is required to movedata over the I/O interface to the memory block 2401 a of the cache. Thesecond organization may be programmable to provide various methods ofassembling and de-assembling words for transfer to and from anindividual memory block. Further, the preferred cache structure has atleast two ports in order to support simultaneous transfers of databetween memory layers and the cache, and between the cache and one ormore data requestors.

The preferred embodiment of the invention performs a memory access uponreceiving a logical address at the controller, the controller determinesif the storage locations of the requesting address is in the memorylayers with which it is associated. The control then translates thelogical address into a gate line select address, a layer enable addressand the portion of the data lines that are to be used in the accesscycle with respect to writing or reading data. In a read access cycle aselected gate line of a memory layer is coupled with the data lines ofthat layer passing to the Sense Amplifiers and then through aprogrammable data line router which is configured as part of the readaccess cycle by data line directives read from configuration memory. Theresulting data from the data line router pass through the test and errorcorrection circuitry and then to a cache from which the read data ispassed on to the requesting source through a programmable I/O interface.If a failure is detected and not corrected, the read cycle is stoppedand the status of the failure is reported to the controller, which inturn makes the existence of the failure known to the requesting source.In a write access performed to the cache, the data is passed from thecache to error coding circuitry and then through the data line router tothe data lines where the data is stored in memory cells coupled to thedata lines and the selected gate line. If a recoverable memory cellfailure is detected during a read or write memory access cycle, thespecific cell failure is passed on to the controller which in turn savesthis information for subsequent determination of reconfiguration of theIC or passes it onto a second control logic which makes thisdetermination and directs the controller to make such changes during thenormal operation or during a startup or maintenance period.

The stacked structure of the invention through vertical interconnectionsenables shorter high density interconnect access to and simplifiedorganization of the various portions of circuitry from several aspectssuch as common access to a central controller or for a plurality ofcircuit elements with common shared interconnections. Verticalinterconnections are also an enabling aspect for the VSI implementationof reconfiguration router circuitry to achieve fail safe error recoveryfrom memory failures during operation in either a dynamic or delayedmethod. This is the case because in planar memory circuitry the physicallayout implementation of reconfiguration circuitry would increase in thenumber of horizontal interconnection layers such that doing so would gobeyond present capabilities of semiconductor fabrication or theoperational performance of the circuit would be unacceptable due todelays resulting from the length of interconnections. It is also clearthat the added reconfiguration circuitry adds cost to the fabrication ofa circuit, this added cost is offset by a high density of fine grainvertical interconnections therein enabling the reconfiguration circuitryto be cost effectively utilized or shared among the memory circuitlayers of an IC due to a near equal physical proximity to all circuitrysegments. Another example of shared circuit utilization in the inventionis the shared use of control logic functions such as sense amplifiersamong the memory arrays of each memory layer wherein a planar memory ICa separate set of sense amplifiers would be required for each memoryarray on the IC which adds significantly to the cost of planar memoryICs.

The invention enables a low cost high density high performance multipleport memory VSI IC that can be vertically integrated with multiplelayers of logic for data processing such as microprocessors, graphicprocessors, database processors, FPGA logic, ASIC logic and othergeneric or application specific logic or optical or MEMS device layers.The use of fine grain vertical interconnections to a plurality of memorylayers allows for the efficient shared use and near equal distancelocation of control and reconfiguration logic to the memory array ofeach memory layer. The shared use of logic enables approximate 50% costreduction in manufacturing costs on a per memory cell basis versusconventional planar memory fabrication methods due to the inventionsability to increase the density of memory cells per IC, therefore, lowerthe ratio of control circuitry per memory cell; a 50% cost reduction isachieved typically when the number of memory layers is four or greater,and thereby, the ratio of control logic circuit area per memory cell ofthe invention is 20% versus a nominal 50% in planar DRAM or flashcircuits. The performance of the invention is nominally 2 to 5 timesfaster than conventional planar memory circuits due to capability of theinvention to use higher performance logic circuit fabrication processesthan those known to be presently used in planar memory circuits becausethe logic layers physical separate from the memory layers, andtherefore, do not require the use of merged fabrication processes whichis known to compromise the performance of present DRAM and flash planarmemory circuits. The performance of the invention is further enhancedversus planar circuit fabrication for example through use of parallelmemory operations in blocks, multi port blocks, gate line segmentation,low leakage memory cell process implementation through SOI [Silicon onInsulator] and differential data line sense amplifier circuits; the useof such performance enhancement techniques when applied to planar memoryICs have been shown not provide the desired level of performance or haveto come at too high a cost.

The controller circuit when implemented for a DRAM memory providesbackground or internal refresh. DRAM circuits require that their memorycells be refreshed periodically. Refresh is accomplished by concurrentlyperforming refresh operations in memory arrays stacks that are not inuse in an ongoing memory access or through multiple ports of a memoryarray stack. Refresh may also be accomplished by increasing the size ofthe memory stack cache allowing refresh cycles to be performed whilememory operations are deferred to the cache.

The benefits of the invention's internal self testing and programmablereconfiguration capability are lower testing costs, higher circuityields and lower failures during the operating life time of the IC. Theinternal test and reconfiguration capability of the invention lowerstest cost by eliminating the current requirement of memory circuits suchas DRAM that several separate tests of the circuit be performed byexpensive external equipment called Automatic Test Equipment. Highercircuit yields result from the use of novel reconfiguration and errorcorrection circuitry that allow a greater number of defective memorycells to be present than would be the case with present memory ICs.

The discussion of the embodiment of the invention is with respect tomemories of common use such as DRAM and flash memories. The invention isnot limited to such embodiments, but can be applied to a wider range ofmemory circuit types such as the anticipated MRAM [Magnetic RandomAccess Memory]. Although MRAM circuits are read by sensing theresistance of a memory cell versus charge or potential of the morecommon memory types, MRAM memory cells still have need of test, errordetection, error recovery and reconfiguration circuitry, and highprecision circuitry for operation as single or multi-level storagecells.

VSI Card PC and Workstation Form Factor

Another embodiment and aspect of the VSI invention is a hand insertionand portable package form factor for VSI IC systems and subsystems.There presently is in use microcontrollers and limited amounts ofelectronic storage embedded in credit card type packages or form factorsand are referred to as SmartCards. There also has been speculation thata PC [Personal Computer] will eventual be reduced to this scale andreferred to as SmartCard PC or Pocket PC, however, no such reduction ofa general purpose computing system such as a PC to a PC SmartCard likeform factor has been demonstrated. The VSI invention enables theelectronic data processing and storage circuitry of what is todayreferred to as a workstation, desktop computer or a lap top computer tobe reduced in physical volume so that it can be packaged in the formfactor of a credit card or similarly sized cards that are commonly usedtoday for commercial transactions. This form factor will herein bereferred to simply as the VSI Card or Card packaging form factor. ThisVSI Card method of packaging the electronics of a computer systemenables novel utility in terms of the portability of the informationstored and processing capability therein that is not presently possible.The VSI Card form factor of the invention uses one or more VSI ICswherein the stacked VSI IC or ICs contain at least a microprocessor orlogic circuitry for data processing or computing, memory of volatile andor non-volatile types, and preferably, high speed wirelesscommunication. The VSI Card is a complete computing environmentsufficient to replace the electronics of what is now a set of planar ICsassembled on PCBs. The VSI Card reduces the I/O count, powerdissipation, packaging costs in comparison to current PCB equivalents,but most importantly, the VSI Card form factor enables the computinghardware and software environment of the user to be independent of anddetachable from peripheral equipment so the VSI Card may be used withnumerous and varying sets of peripherals. The VSI Card can integrateoptical and MEMS functions not only as part of the VSI IC integrationbut as part of the physical card packaging such as optical input oroutput through the surface of the package. The VSI Card is plugged andunplugged into peripherals as needed enhancing the utility and securityof the information on the VSI Card. The transmission of signals to andfrom the Card, or I/O, is through a physical contact or wireless in theform of radio frequency or optical wavelengths.

The Card packaging of such a significant amount of computing electronicsis enabled by the high circuit densities of the VSI invention. It shouldbe noted that the electronic content of computing systems generallyreferred to as PCs [Personal Computers] or workstations has risen in adirectly proportional manner to the rise of planar integrated circuitdensity and is expected to continue to do so. And, as of the present,the amount of circuitry necessary to provide the computing performanceand capability of these computing systems currently comprise so manyplanar ICs that the insertion into a card package cannot be enabled froma physical or operational perspective. The VSI Card reduces the I/Ointerconnections versus planar ICs through vertical interconnectionsbetween circuit layers. The Card reduces power also through thereduction in the number of I/Os, since I/O drives constitute asignificant percentage of the power dissipation of a planar IC. The Cardreduces cost by eliminating or reducing the packaging, testing andhandling of planar ICs.

There are three principle benefits provided as a result of thecapability to reduce the number of ICs of present and future state ofthe art computing systems such as PCs or workstations that are derivedthrough the use of the VSI invention to enable a VSI Card packaging formfactor. These are portability, power reduction and lower computingequipment utilization cost.

The benefit of Card portability is a capability that enables thecomputing electronics to be plugged into various types of peripheralequipment which presently require that the computing electronics beembedded with such peripheral equipment. Separating what is currentlythe control electronics of a computing system such as a PC, work stationor other such computing electronics from the peripherals of thatcomputing system allows the sharing of both the processing capabilityand the memory among as many such computing systems that are designed toreceive this card. Examples of such peripheral equipment are personalcomputer or workstation display monitors, keyboards, storage devices,etc., cellular phones, Personal Digital Assistances [PDAs], TVs, audioand video equipment, consumer appliances. Such portability enables thepersonal data that is stored on the card to be used or modified atmultiple physical locations and enables a level of physical security ofthe information stored on the card that does not exist presently.

The benefit of Card power reduction is derived from the reduction orelimination of signal drivers from the ICs of the card. Signal driverson present day microprocessors, graphics processors, encryption, voiceanalysis and memory circuitry can number in the thousands and contributea majority of the power that must be dissipated from planar ICs. Whereaspower reduction is widely recognized as an IC operating benefitpresently, the ability to increase the amount of circuitry per unitvolume while reducing power, due to I/O power reductions, is unique tothe VSI invention and specifically to the application of highperformance card computing form factors.

The benefit of Card computing equipment utilization results from thephysical separation of the computing electronics from the peripheralequipment normally associated with what is presently a computer systemor more broadly equipment that performs a function be it a desktopcomputer, a car, an airplane, manufacturing equipment or sensing andanalysis equipment to name a few examples. Presently computingelectronics is embedded or integrally assembled as part of a wide rangeof equipment. In general today the cost of computing electronics,without including the cost of the power supply and box enclosurepresently used, is less than the peripheral equipment with which it isassociated. Therefore, in the case where equipment is used by multipleindividuals or users and these users have unique electronically storedinformation necessary to operate the equipment which would normally makethe equipment captive or nearly so to one single user, this would be nolonger the case. The equipment now has a higher potential utilization byvirtue of its separation from any one user, and therefore, a lower costof utilization per user because it can be shared or it has a sharedutilization. Secondly, obsolescence of peripheral equipment is often theresult of the obsolescence of the computing electronic assembled withthem, therefore, the separation of the computing electronics into theVSI Card packaging form factor enables longer utilization of theperipheral equipment.

Such peripheral equipment, or simply equipment, presently can be diskstorage devices, networking equipment with wired [metal and optical] orwireless interfaces, faxing, copying, imaging, scanning, photoreproduction, etc. The VSI Card and peripheral equipment separationbenefit also includes equipment relating to manufacturing and industrialequipment where computing equipment is used to control the equipment asin the examples of robot assembly, inspection, semiconductor processingequipment, chemical processing equipment, etc. This separation benefitalso includes equipment for monitoring and control of a facility such asan office building, industrial plant or home; here computing equipmentis used to monitor and control peripheral equipment such as videocameras, door access security, elevators, furnaces, air conditioners,air quality sensors, etc. The separation benefit enables the computingelectronics to be exchanged or up graded for such reasons asperformance, maintenance, security or improved capabilities withoutaffecting the physical cabling or fixtures used presently with computingequipment that uses the well know box or electronic stack form factor.

The VSI Card separation benefit enables multiple Card computingelectronics to use the same peripherals in either in a serial or clustermanner. This allows the cost of peripheral equipment to be shared overseveral Card computing users serially or from time to time as needed orconcurrently where some number of Cards on a given instance areconnected to the same peripheral equipment. The concurrent use aspect ofthe Card computing electronics enables a form of what is now commonlyreferred to as cluster or multiprocessor computing where multiple Cardsuse the peripheral equipment they are inserted into as a means tocommunicate between themselves to perform specific tasks.

The VSI Card can be used as a packaging means for the selling ofsoftware to prevent its fraudulent use on other than the intendedcomputing system or as means to guarantee to the customer certainperformance and or operating capabilities. Software is presently sold onpassive media or over the internet and its use thereafter is beyond thecontrol of the software manufacturer. The use of the VSI Card as apackaging means of the software allows the software manufacturer tocontrol the hardware environment wherein the product software is used.This means that the use of software manufacturers product softwarecannot be done except through use of the VSI Card and that it can onlybe updated through a VSI Card that packages the software, this is adegree of security for the software manufacturers that does notpresently exist.

VSI Image and E-M Sensor Component

The VSI invention enables the making of high speed, low noise andlithographically limited high resolution image or EM [Electro-Magnetic]radiation sensors. This is done by separating the imaging array [CCD,photodiode or wavelength sensitive element array] as a top circuit layeror layers of a VSI Component and using fine grain verticalinterconnections to connect image or EM sensing elements individually orlarger organizations such as a line of imaging sensor elements to analogand digital circuitry on circuit layers directly below the imaging or EMsensor layer.

In this VSI invention CCD, photodiode or wavelength sensitive sensorelements or devices can be closely coupled to processing circuitry suchas A/Ds, analog circuitry, and digital logic which can be made from ICprocesses independent of the processes used to make the image or EMsensor layer, and therefore, enabling design of such VSI components asphoto imaging electronic components or communication Optical-Electronicconverters that couple image or EM sensor elements with processingcircuitry for any number of possible design objectives such as cost,performance or image or wavelength resolution without the manufacturinglimitations that presently exist regarding the integration of the sensorelements with the type of processing electronics selected. Secondly, theamount or density of processing circuitry for processing the output froma single or group of image or EM sensors can be increased over thepresent art with the addition beneath the image or EM sensor layer ofmore processing circuit layers. Further, large amounts of memorycircuitry can also be integrated into a VSI image processing component,the ability to buffer the image data on the VSI image component allowsthe image data to be internally processed or down loaded in a non realtime rate or a rate other than the rate of EM sensor data generation.

The separation of the image or EM sensor layer[s], and the EM sensorinterface and processing circuitry on independent circuit layersprovides a unique level of noise isolation versus planar image sensorswhere noise generated by the processing circuitry directly couplesthrough the common substrate of a planar IC to the image sensorelements. Further, additional noise isolation enhancement can beemployed through the choice of semiconductor process and technology usedto fabricate the EM sensor processing circuitry such as BiCMOS processor GaAs technology versus again the common substrate and fabricationtechnology used to make a planar image or EM sensor IC.

The resolution of the image or EM sensor is a direct result of the sizeof the individual sensor elements and the number of sensors in the EMsensing array. The scaling of the size of the EM sensing elements of theVSI invention is uniquely limited only by fabrication process capabilityand not proximity to processing circuitry as in planar EM sensorcircuits. Secondly, the number of image or EM sensing elements is adesign choice since sensor processing circuitry for any number of sensorelements used is immediately below the sensor elements, further thedistance of separation of each image or EM sensor element ororganization of elements in constant no matter how large the imagearray.

Additionally, the distance from the a single EM sensor element ororganization of elements to processing circuitry is no longer a resultof the row and column size of the image array, but is determined bydesign choice, since all image processing circuitry can be positionedimmediately below and as close as a few microns in verticalinterconnection distance through one or a few circuit layers.

FIG. 25A shows a cross-section of a VSI EM sensor component with imageor EM sensors 2501 a, 2502 a separated by a dielectric and or EMisolation trench 2503 a and sensor signal output contact 2504 a formedpreferably during bonding of the sensor layer as a verticalinterconnection to processing electronic and or memory circuit layers2505 a. The EM sensors of FIG. 25A and FIG. 25B have applications notonly for imaging applications but also communications. Wherein in thecomponents shown in these figures can be used in communication systemsfor single wavelength Optical to Electronic conversion or DWDM [DenseWavelength Division Multiplexing] where a number of wavelength signalsare simultaneously converted from optical to electronic form.

A further advantage of the VSI invention is the ability to use multipleEM radiation sensor circuit layers of varying materials that aresensitive to different radiation wavelengths such as Infrared, visible,Ultraviolet and X-ray wherein such wavelength absorbing materials arestacked to form an imaging sensor and where the order of the stacking ofthese materials is done in a manner to optimize the preference to theirrelative radiation wavelength absorption and transmission rates to anincoming radiation source. This is to say that the material with thehigher transmission rates relative to the other wavelengths of interestwill be positioned to be exposed first to the radiation source.

Wavelength or wave band specific EM radiation sensor elements onseparate and adjacent layers is shown in cross-section in FIG. 25b .Radiation sensor layers 2501 b, 2502 b, 2503 b are bonded in the samemanner as other circuit layers and through which separate verticalinterconnections 2504 b, 2505 b and 2506 b from the image sensorelements in an image array layer to processing circuitry 2507 b thatenables the output of the image devices to be processed simultaneouslyor serially as preferred by the design of the circuitry. Electrical andEM isolation trench 2511 b separate each sensor stack. The bonding ofthe sensor element layers is preferably done by metal diffusion bonding;which would also during the bond process form the verticalinterconnections 2508 b, 2509 b, 2510 b junctions between each imagesensor layer. An example of a VSI component using an array of multiplevisible image sensor layers is a video imaging component; and, anexample of a VSI component using multiple waveband specific EM sensorarray, is an optical fiber communications where an information signalsare transmitted at multiple wavelengths and referred to as WDM or DWDM.

VSI FPGA IC and Method of Making

The VSI invention enables the making of high density FPGA [FieldProgrammable Gate Arrays] by the structural separation of its commonplanar circuit constituents of configurable logic, IP [IntellectualProperty] logic, configurable routing logic and or programming memoryinto two or more VSI circuit layers. Present planar FPGA technology isrestricted in gate density per IC due to lithographic die imagefabrication process restrictions, the density of configuration routingcircuitry, the incorporation of IP and the amount of programming contextmemory. The rapidly increasing cost of semiconductor fabrication masksis presently limiting the number or variety of planar FPGA designs thatare fabricated or brought to market; the high fabrication mask costscannot be recovered from most low volume FPGA designs. This aspect ofthe VSI invention is not limited to the FPGAs but applies to the broaderclass of programmable logic referred to as PLDs [Programmable LogicDevices], and including CPLDs [Complex Programmable Devices].

Planar FPGA circuits can be thought to consist of configurable logic,configurable routing interconnections and programming context memory,programming context memory will be hereafter referred to as contextmemory. Context memory circuitry holds the programming or configurationstate information for configuring the logic functions and routinginterconnections and is also referred to as context information or data.The context memory circuitry may be implemented in a ROM, a write oncetechnology or a rewriteable memory technology. Planar FPGA circuits arecomplex circuits. A primary value of planar FPGA circuits is thatbecause they are programmable they have broad application range orutilization, and therefore, have a lower unit cost resulting from higherproduction volumes due to their broader application range orutilization. A well known restriction of planar FPGA circuits is thatall FPGA circuit designs have a limited range in the amounts ofprogrammable logic, routing and memory resources; and if the FPGAcircuit is a physically large die, the performance of the FPGA isreduced due to signal transmission delay across the die. Due to highdevelopment costs, there are few application specific planar FPGAcircuits [so called low volume FPGA circuits] or FPGA circuits thatinclude application specific hardwired IP functions. The inclusion ofhardwired IP functions reduces the configurable logic resources, breathof application utilization and results in significant increased costsper circuit due lower production volumes.

VSI FPGA components enable the programmable gate density, configurablerouting interconnections and context memory to be separated as circuitlayers, and therefore, the design and capacity of gate density,configurable routing interconnect and context memory can be implementedindependently per circuit layer. Further, the addition of IP per layercan be added. Of first importance, if the circuit layers to be used tofabricate a VSI FPGA IC for a specific application have completedphysical designs or already have been fabricated or exist as inventorywafers of library as part of a FPGA development platform, then the VSIFPGA can be fabricated without requiring circuit design, mask tooling[NRE None Recurring Engineering] charges or a semiconductor fabricationcycle. The VSI FPGA eliminates and or reduces four primary problemsfacing FPGA planar IC which are development time, gate and routingdensity, custom design NRE and low volume fabrication costs. The VSIapproach to FPGA or ASIC IC development and fabrication is significantlyat variance to conventional planar engineering and fabrication methodswith the important benefits of significant reductions in costs and timeto market [wherein time to market time savings result from eliminationof conventional IC development delays and reduction of fabricationdelay]. The VSI invention achieves these results through its capabilityto separate or partition circuitry types to separate circuit layers, theVSI fabrication process simplicity which does not require planar circuitfabrication processing and the VSI fabrication process capability to useexisting or inventory circuit wafers. The VSI FPGA IC may take the formof a standalone IC or component, or it may be incorporated into a largerVSI component with other electronic, optical circuit layers or MEMSdevice layers.

The primary objective of the VSI FPGA invention is to decouple thehardware IC design and fabrication process from the design of anapplication specific FPGA IC. The preferred embodiment is that all ofthe circuit layers of a VSI FPGA be available for use from an inventorysource. It is also an embodiment of the VSI FPGA that one or morecircuit layers may require design and fabrication, however, this stillresults in significant application IC development time and fabricationcost reductions. Other objectives of the VSI FPGA invention are variableprogrammable gate density per VSI component through the use of multipleprogrammable gate circuit layers, higher density programmable routingper VSI component through vertical interconnection gate routing andbackside horizontal interconnections, option to change or vary withoutaffecting hardware design per VSI the use of IP such as microprocessor,DSPs, CAM, or SERDES, and the capability to increase the availablecontext memory per VSI component to enable in circuit programmingchanges of the programmable gates or routing interconnections.

Even through the VSI FPGA is composed of numerous circuit layers thebenefit of the VSI fabrication process for the VSI FPGA component is anintegration density that is greater than a planar circuit equivalent,and therefore, higher performance due to shorter interconnectionlengths, and lower power due to shorter interconnection lengths and theneed for fewer I/O off-chip circuit drivers. The need for fewer I/Ooff-chip circuit drivers resulting from the level of integration of theVSI FPGA, and therefore, the need to connect to fewer separate planarICs. The preferred embodiment of the VSI FPGA uses thermal diffusionhigh precision alignment circuit substrate bonding and sub 2 μm pitchfine grain vertical interconnections enable the VSI FPGA integration.

The VSI FPGA routing interconnect density can provide an increase of 2×to 4× more than planar routing due to the inventions ability tofabricate horizontal interconnect on the backside of each circuit layerequal to the same density as on the front side, and the ability tofabricate fine grain vertical interconnections several times the densityof horizontal interconnection layers, and therefore, allowing theimplementation of such vertical interconnect structures as datapaths orbuses with more than 512 transmission lines and in excess of 4,000transmission lines without increasing the number of horizontalinterconnection layers. This is done by using the VSI fabricationprocess to form fine grain vertical interconnections to form local andglobal busing between programmable logic blocks of an arbitrary numbercircuit layers of programmable logic blocks. Further, local verticalinterconnections are used to couple circuitry on two or more circuitlayers to form a logic block spanning vertically two or more circuitlayers or for busing between vertically adjacent logic blocks. FPGAprogramming information can be held on separate memory register circuitlayers with the capability through global fine grain vertical bussing toprovide access to a range of memory register locations which can beaddressed and read selectively into specific FPGA logic blocks andthereby change their functions.

The VSI FPGA invention also enables the inclusion of self test or ATEcircuit layers and yield enhancement error reconfiguration circuitlayers. These circuit layers in the preferred embodiment can be added tothe VSI FPGA component without affecting the design of the existing VSIFPGA circuit layers. These circuit layers allow for a greater level ofcircuit testing at a fixed cost and the ability to reconfigureprogrammable gate and routing interconnection circuit layers whencircuit defects are detected in a manner that is transparent or nearlyso to the subsequent use of the IC. The error reconfiguration circuitlayers provide redundant routing interconnection circuitry that can besubstituted for defective portions of a programmable gate or routinginterconnection circuit layer. The capability of the VSI FPGA to addself test and reconfiguration circuit layers becomes most important asthe number of circuit layers used in the VSI FPGA increase and therebyincrease the IC test duration and adversely affect the IC yield. Theerror reconfiguration circuit layers are programmed to replace variousdefective portions of programmable gate or routing interconnectioncircuit layers as a result of the test data derived from the self testor ATE circuit layer. The programming of the error reconfigurationcircuit layer or layers is performed by control circuitry on the errorreconfiguration circuit layer, but this control circuitry mayalternately be part of the self test or ATE circuit layers.

It is important to point out that in the preferred embodiment of the VSIFPGA, the number of programmable gate circuit layers, IP circuit layers,programmable routing circuit layers and context memory circuit layerscan be increased or decreased as required to meet application specificrequirements without affecting the design of these circuit layers. Sinceonly the VSI fabrication process steps are required in order tofabricate a VSI FPGA component or circuit layer group for subsequentinsertion into a layer VSI component, there is not the existingrequirement for circuit design changes, NRE tooling or circuitfabrication. Further, the insertion of self test and errorreconfiguration circuit layers can be done in a similar manner with thebenefit realized through the short VSI fabrication cycle and additionalIC capability.

The circuit layers needed for a VSI FPGA may not all be available fromthe library of a VSI development platform or an inventory of VSI FPGAcircuit layers, and therefore, the design and fabrication of one or moreVSI FPGA circuit layers may be necessary. When this is the case, thedesign of such a circuit layer is clearly less complex and less costlythan the complexity of integrating such additional circuitry into aplanar design which affects the physical layout design of the existcircuitry of the planar IC. The VSI FPGA capability to vary its circuitresource capacities with little or no requirement for circuit layerdesign and fabrication has the following novel results: it uniquelyreduces IC fabrication cycle time and cost of the VSI IC fabricationprocess which are significantly less; it enables lower volumeapplication specific FPGA circuits to be designed and fabricated thatfor the present cost structure of FPGA manufacturing is development timeand cost prohibitive; and, it enables low cost IC developmentexperimentation or “what if” engineering exercises which are so veryimportant in lowering the risk to the development of new product ideasand new business growth.

FIG. 26A shows in cross-section a VSI FPGA component IC 2603 a whereinprogrammable logic, IP and programmable routing interconnections consistof two or more circuit layers 2601 a and context memory consists of oneor more volatile and or non-volatile memory circuit layers 2602 a. Theremay be memory cells incorporated in with the programmable logic layers2601 a, the context memory circuit layers are used to retain variousprogramming states which can be loaded at high speed through densevertical interconnections as needed into the programmable logic orrouting interconnections. The FIG. 26A circuit may also incorporate ATEand reconfiguration circuit layers for yield enhancement of the totalVSI component. The VSI circuit layers shown in FIG. 26A can be used as asub-system and incorporated into a larger VSI component IC or be amember of a VSI platform library as post fabricated VSI circuit waferinventory for integration into a future VSI IC or VSI ASIC.

FIG. 26B shows in cross-section a VSI FPGA component IC 2604 b whereinprogrammable logic circuit layer types and IP consist of several circuitlayers 2601 b, programmable routing interconnections consist of severalcircuit layers 2602 b and context memory consists of several circuitlayers or memory circuit group incorporating yield enhancement circuitry2603 b. The FIG. 26B circuit may also incorporate ATE andreconfiguration circuit layers for yield enhancement of the total VSIcomponent.

The VSI invention further enables the use of fuses and, anti-fuses orother type of write once technology for the programming the functions ofinterconnections between logic blocks implemented in the logic layers orthe routing interconnection layers or both; the use of one timeprogrammable technology may replace the use of all or part of the memorycircuit layers or to be used in combination. This is accomplished byusing fuse programming circuit layers and fine grain verticalinterconnections to enable the blowing specific fuses on at specificlocations on one or more logic block circuit layers. This uniquelyenables the interconnection and circuit logic structures of the fuseblowing circuit layers to be used to program an arbitrary number oflogic block circuit layers.

VSI Internet Protocol [IP] Communication System

Conventional Internet Protocol [IP] processors [referred to as routersor network processors] analyze the pack messages in coming from one highspeed connection [typically a fiber optic transmission line] and as aresult of the analysis collect information about the message anddetermine an out going communication line to forward the message. Thismessage is then transferred to the appropriate out going transmissionline or lines by means of a switch which may be implemented based on amultiple port memory or as a n×n non-blocking cross bar switch.

The VSI IP communication processor component or IC shown in FIG. 27combines in the preferred embodiment as one die, one or more IP networkprocessors 2701, multiple circuit layers of FPGA logic 2702, multiplecircuit layers of CAM [Content Addressable Memory] 2703, conventionalrandom access memory layers 2704, serial I/O serializer deserializerlogic layer or layers 2705, and two or more very wide fine grainvertical buses 2706 connecting the IP VSI component circuit layers whereeach vertical bus may consist of several hundred to several thousand buslines. The VSI IP communication processor shown as a VSI IC circuitlayer structure in FIG. 27, is novel because it combines into one dieall the fundamental functional circuit types traditionally used to routeand switch an IP message in circuit densities per circuit type that areseveral times greater than that presently possible with planar ICtechnology, and heretofore such implementations have only been possibleas multiple planar ICs if at all. The VSI IP communication processorincorporates optical serial line input and output, incorporating thetraditionally separate switching logic. The use of both networkprocessors and FPGA circuit layers is an implementation decision and isnot a limitation on the IP VSI component illustrated herein.

The VSI IP communication processor can incorporate varying amounts ofCAM and conventional memory to process an IP message depending on thedesign capacity objective of the VSI IP component and beyond any suchcapacity available from a planar IC for any future point in theintegration progression for ICs. The preferred embodiment of the VSI IPcommunication processor incorporates on a separate layer multiple serialinput and output logic for internal circuit serializing anddeserializing IP messages from communication lines; by doing so, thisgreatly reduces the total pin count and power dissipation of the VSIcomponent versus such a system implemented as some number of planar ICs.The preferred embodiment of the VSI IP communication processor achievesits most significant advantage through the use of multiple arbitrarywide high speed vertical buses 2706 that allow for a large number ofpaths from IP message processors to memory and to serial I/O, and VSItest and yield enhancement logic 2707. The VSI IP communicationprocessor also may have conventional busing interfaces for wired orwireless communications to additional VSI IP communication processorsand conventional subsystem components.

The benefits of the VSI IP communication processor are nominally a costreduction of 10× versus equivalent circuit implementations by multipleplanar IC IP communication electronic assemblies, a 5× performanceenhancement, and a 10× reduction in power dissipation. These primarybenefits are a direct result of the multiple wide high bandwidth finegrain internal vertical buses, fewer off-chip I/O circuit drivers, netshorter interconnection lengths between and yield enhancementreconfiguration circuit logic.

VSI n×n Cross Bar Integration

The mention herein of an integrated n×n non-blocking crossbar deserves alittle additional discussion. Larger systems like multi-processors orinternet IP routers are collections of separately packaged andinterconnected high integration processor ICs where the most significantportion of the manufacturing cost of these systems is the wiringinterconnections [datapaths] between these ICs consisting of packages,sockets, low integration crossbar control circuits, PCBs and PCBconnectors. The implementation of these high cost low integrationdatapaths are reduced to less than 1 mm² for each VSI processor circuitlayer, so for the interconnection of 16 processor system with aintegrated 16×16 non-blocking cross bar interconnection, the cost isabout $2-3, or approximately a 1000× cost reduction, not to mentionsignificant power dissipation reduction and performance improvement.

Integration of multiple processors with a n×n crossbar bus system is anintegration challenge for planar IC technology even withoutconsideration of the requirements for embedded processor memory. Thistype of data path interconnect problem also is a characteristic ofinternet switches & routers, and the VSI invention enables thefabrication of a single chip high-end router.

A VSI n×n non-blocking crossbar switch is implemented as a verticallyinterconnecting set of buses where processing logic of each circuitlayer that is a port to the crossbar switch has interconnect access toany of the n-ports of the switch. In present planar IC implementation ofn×n crossbar switches data processing circuitry has access to only oneor two ports of the n×n switch. The VSI n×n switch simplifies access tothe switch by providing access to all or most of the ports of theswitch. The VSI n×n switch increases throughput performance by enablingaccess to more than one switch port at one time to achieve a higherbandwidth per transmission.

VSI Passive and Analog Device Programmable Array

The VSI invention uniquely enables a method of making programmablepassive and analog stacked circuits. This is done by fabricating one ormore circuit layers of passive devices [resistors, capacitors andinductors] and vertically interconnecting these devices to one or morecircuit layers of programmable routing interconnections designed formaking and or remaking interconnections between the passive devices andthe circuitry on other circuit layers. This aspect of the VSI inventionis herein called a programmable passive array or PPA. Passive circuitelements may be fabricated from MEMS processes such as in thefabrication of inductors. The passive circuit elements are preferablyfabricated on a semiconductor substrate which would allow fabrication ofactive circuit elements if desired such as SOI, GaAs, InP or GaN.

This same approach can be used to make programmable analog circuitarrays. This is done by fabricating one or more circuit layers of analogelements and vertically interconnecting these elements to one or morecircuit layers of programmable routing interconnections designed formaking and or remaking interconnections between the analog devices andthe circuitry on other circuit layers. This herein is called aprogrammable analog array or PAA.

It is also an aspect of the VSI invention that PPA and PAA circuitlayers be combined in a common VSI component or circuit stack, whereinthe same programmable routing interconnections circuit layers can beused to form vertical interconnections to both the passive and analogcircuit elements. The various passive and analog circuit elements thatmay be integrated into an IC are often fabricated with processes thatcannot be combined in the fabrication of a planar IC, this is often theprimary limitation for the fabrication of a class of planar ICs that arebroadly referred to as a SoC or System on Chip. The VSI process allowsthe various fabrication processes to be used to their full extent butsegregated to separate circuit layers. In this manner the benefit of afabrication process can be realized as needed without comprise or addedfabrication complexity that would result if these processes were mergedon one substrate.

It is also an aspect of the VSI invention that in the design of PPA andPAA circuit layers a redundant or spare passive, analog and routinginterconnections be used to either increase the yield of the PPA and PAAcircuit layers or to provide a means to tune the final circuit bychanging the selection of PPA or PAA elements with the expectation thatthe various individual passive or analog elements will have operationalor performance variations. The yield of the PPA or PAA circuit layerswould be improved through use of a test means such as an internal selftest or ATE circuit layer which would test PPA, PAA and routinginterconnections to determine if circuit defects are present. The use ofdefective PPA or PAA elements is avoided by changing the programmablerouting interconnections from a defective element to its spare. The useof defective routing interconnections is avoided by changing theprogrammable routing interconnections to an alternate interconnectionpath or by use of spare programmable routing interconnectionscorresponding to the defective one.

It is also an aspect of the VSI invention of the PPA circuit layers thatthe passive elements be fabricated with conventional IC fabricationmeans on the backside of either an analog circuit layer or theprogrammable routing interconnection circuit layers. Backsidefabrication may not be possible for certain passive element types due toan incompatibility of certain process steps with respect to an existingset of circuit layers of a VSI substrate stack, and therefore, mayrequire the fabrication of the passive electronic circuitry before thefabrication of the active circuitry on the same substrate and before itsaddition to a VSI IC stack.

It is important to also keep in mind that not all PPA and PAAfabrication processes have the same cost, and that there is a wide rangein costs of such fabrication processes. It is therefore another aspectof the VSI invention that due to its capability to separate fabricationprocesses per circuit layer then process costs are minimized to an asneed fabrication sequence. An example in a planar circuit is thefabrication of an IC wherein approximately one half of the IC area usesa lower cost process and the other half of area uses a premium costprocess, since the cost of a fabrication process is based on unit area,the cost of the planar IC could be approximately twice the cost of twoseparate fabricated circuit layers each of area approximately one halfof the planar IC.

Further, it is also an aspect of the VSI invention that passive andanalog circuit layers be connected without a programmable routinginterconnection wherein the VSI fabricated vertical interconnections arededicated from passive and or analog circuit layers to other circuitlayers of a VSI component. The use of a switching circuit layer withpassive and analog arrays is not required, if there is no need that thevertical interconnections to various passive or analog elements of onecircuit layer from other circuit layers to be alterable. This is anotherembodiment of the VSI invention wherein vertical interconnections frompassive or analog circuit layers have fixed interconnections to othercircuit layers. These fixed interconnections may be formed at the timethe passive or analog circuit substrate is fabricated or at a subsequenttime such as during backside processing wherein vertical and horizontalinterconnections may be fabricated for an application specific design.

It will be appreciated by those of ordinary skill in the art that theinvention can be embodied in other specific forms without departing fromthe spirit or essential character thereof. The presently disclosedembodiments are therefore considered in all respects to be illustrativeand not restrictive. The scope of the invention is indicated by theappended claims rather than the foregoing description, and all changeswhich come within the meaning and range of equivalents thereof areintended to be embraced therein.

1.-20. (canceled)
 21. A method of making a stacked integrated circuit,comprising: stacking a plurality of closely-coupled integrated circuitlayers in relation to one another; and interconnecting at least two ofthe plurality of closely-coupled integrated circuit layers using aplurality of vertical interconnections in a standardized placement,wherein the plurality of closely-coupled integrated circuit layerscomprise at least a logic layer and a memory layer that have a samestandardized placement interconnection pattern as corresponding logiclayer and memory layer integrated circuit layers of at least onedifferent stacked integrated circuit having a different design than saidstacked integrated circuit; wherein a unique integrated circuit layer ispresent in only one of the stack of integrated circuits and thedifferent stacked integrated circuit, and wherein the unique integratedcircuit layer, the stacked integrated circuit and the different stackedintegrated circuit share a same standardized placement interconnectionpattern.
 22. The method of claim 21, wherein, in said stacking step, theclosely-coupled integrated circuit layers comprise first stackedintegrated circuit layers that are instances of a set of designs ofdifferent mutually interchangeable stacked integrated circuit layers,the first stacked integrated circuit layers consisting of a first subsetof the set of designs of different mutually interchangeable stackedintegrated circuit layers, and the at least one different stackedintegrated circuit comprising second stacked integrated circuit layersthat are instances of the same set of designs of different mutuallyinterchangeable stacked integrated circuit layers, the second stackedintegrated circuit layers consisting of a second subset of the set ofdesigns of different mutually interchangeable stacked integrated circuitlayers, wherein at least one of: the first subset is different than thesecond subset; the first subset is the same as the second subset, andeach of the stacked integrated circuit and the at least one differentstacked integrated circuit comprises at least a plural number N ofstacked integrated circuit layers, but for at least one number N, an Nthstacked integrated circuit layer counting from a bottom-most layer ofthe stacked integrated circuit and an Nth stacked integrated circuitlayer counting from a bottom-most layer of the at least one differentstacked integrated circuit are instances of different designs of the setof designs of different mutually interchangeable stacked integratedcircuit layers.
 23. The method of claim 21, wherein, in said stackingstep, the closely-coupled integrated circuit layers comprise stackedintegrated circuit layers that are instances of a first subset of a setof designs of different mutually interchangeable stacked integratedcircuit layers, and the at least one different stacked integratedcircuit comprises stacked integrated circuit layers that are instancesof a second subset of the set of designs of different mutuallyinterchangeable stacked integrated circuit layers, wherein the firstsubset is different than the second subset.
 24. The method of claim 21,wherein, in said stacking step, the closely-coupled integrated circuitlayers comprise first stacked integrated circuit layers that areinstances of a first subset of a set of designs of different mutuallyinterchangeable stacked integrated circuit layers, and wherein the atleast one different stacked integrated circuit comprises second stackedintegrated circuit layers that are instances of a second subset of theset of designs of different mutually interchangeable stacked integratedcircuit layers, wherein the first subset is the same as the secondsubset, and each of the stacked integrated circuit and the at least onedifferent stacked integrated circuit comprises at least a plural numberN of stacked integrated circuit layers, but for at least one number N,an Nth stacked integrated circuit layer counting from a bottom-mostlayer of the stacked integrated circuit and an Nth stacked integratedcircuit layer counting from a bottom-most layer of the at least onedifferent stacked integrated circuit are instances of different designsof the set of designs of different mutually interchangeable stackedintegrated circuit layers.
 25. The method of claim 21, wherein, in saidstacking step, at least one of the closely-coupled integrated circuitlayers comprises stress balanced dielectrics.